softGlue Release Notes

Release 2-0 (Sept 24, 2010)

• Inverted outputs have been deleted from all FPGA components. Instead signal inversion is accomplished by appending an asterisk to the signal name specified for an input (or for a field I/O output, which behaves as an input).
• All 48 I/O bits are supported by both field inputs and field outputs, and the I/O directions are specified at boot time. If a bit is set for output, its digital value is routed to the field input, so that the bit can generate interrupts. With this change, all IP-EP20x modules should be supported, though this hasn't been tested, and databases and MEDM displays are provided only for the IP-EP201 (48 TTL bits).
• Added an 8 MHz clock component.
• Added more gates, added buffers (primarily so users don't have to use a logic gate simply to get an EPICS-written value fanned to more than one input).
• Added the secondary module, Octupole, which contains two 32-bit shift registers.
• Down counters and divide-by-N components are now 32 bit.
• User can control the polling period for field I/O bits.
• No longer maintain separate read rates for connected and unconnected signals, and cause signal-show display to be driven by a software event whose number is specified at boot time, rather than being periodically scanned. These and other changes simplify signal-name processing and speeds it up significantly. (Previously, two sCalcout records were processed every time a signal name was changed. Now none are.)

Release 1-1 (June 14, 2010)

• Added the ability to load FPGA content at boot time, from a file, via the IP bus.
• Modified the recommended method of loading EPICS support. Now, user is expected to load the database directly from the softGlue module, so it's more likely to agree with FPGA content also loaded from softGlue.
• Renamed ip1k125 to IP_EP200 or IP_EP201.
• Now supporting 16 field-input bits, and 16-field output bits.
• Added 32-bit up counters.
• Added limited support for using Drag-And-Drop to connect signals. If the string written to a signal is the PVname of some other signal pertaining to the same IP-EP201 module, device support will replace the PVname with the string value of the PV. This connects signals only if the Drag-And-Drop source PV was not numeric, and not an empty string.
• Tighten up notion of legal signal names: leading spaces removed; for outputs, leading decimal digits alse removed. Added PINI=YES to *Signal PV's, so rules are enforced also boot time.
• Input signal names ending with '*' are allowed, denote the same signal as the same signal name without a trailing '*', and indicate that the signal value is to be run through an inverter before being applied to the circuit element.
• use msi to build partially resolved databases, so user can supply their own P and H macros, without having to supply everything else.
• interrupt handling worked only when both edges were enabled
• user can modify interrupt enables, and poll time for non-interrupting field I/O signals, at run time.
• interrupt handler throttles interrupts
• included records for interrupts to drive; implemented GUI for users to manage this.
• added BURT request file to save all of softGlue
• added 8 MHz clock
• decrement user's down-counter N value before writing to FPGA
• Documentation and examples

Release 1-0 (Mar. 30, 2010)

• Initial release