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<== Date ==> | <== Thread ==> |
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Subject: | VR9 VME64 Problems |
From: | "Darrell Nineham" <[email protected]> |
To: | <[email protected]> |
Date: | Wed, 13 Jul 2005 16:15:21 +0100 |
Any
one have any experience with the VR9 VME64 processor ?
Not
trying to run EPICS, just accessing VME Cards via MBLT under Red Hat Linux
?
Any
help/thoughts greatly appreciated with below problems ?
Darrell Nineham Hytec Electronics Ltd. Tel: +44 (0) 118 975 7770 Fax: +44 (0) 118 975 7566 Web: www.hytec-electronics.co.uk ++++++++++++++++++++++++++++++++++++++++++++ This email and any files transmitted with it are confidential and intended solely for the use of the individual or entity to whom they are addressed. If you have received this email in error, please notify the sender immediately. The views expressed in the message are those of the individual author and may not necessarily represent the views of Hytec Electronics Ltd. -----Original Message-----
From: Darrell Nineham [mailto:[email protected]] Sent: 13 July 2005 12:42 To: 'Claudia Schleich' Cc: Alan ([email protected]); [email protected]; [email protected]; Mel Newman ([email protected]) Subject: MBLT Querries Hi
Claudia,
We have a couple of
problems in the way the VR9 MBLT works......
Problem 1. There
is an enormous delay 250uS between the issue of an MBLT read and it
actually starting.
Working
through the below code extract and comparing to logic analyser output (MBLT
Timing Diagram 01 - Start Delay.jpg) ....
// Wait for the
DMA Request Flag
result = Hy8002RegRead( A16channel, FIRST_SLOT_USED, Hy8002F_IP_STATUS, &iDataRead); while((iDataRead & Hy8002F_IP_DMA_A) == 0) { result = Hy8002RegRead( A16channel, FIRST_SLOT_USED, Hy8002F_IP_STATUS, &iDataRead); } // Insert Extra
Read so AS can be used as a start time on logic
analyser
result =
Hy8002RegRead( A16channel, FIRST_SLOT_USED, Hy8002F_IP_STATUS,
&iDataRead);
//
MBLT Read of all ADC Data
result =
VmeRead( A24D64channel, lVMESlotBase24[FIRST_SLOT_USED - 1] + Hy8407_ADC_REG,
512, &bReadData);
The while( ) loop exits when the DMAReq goes low, we
then do an extra read to use an indication of start
time for the logic analyser, so we know the delay is not due to the loop
etc) and straight away call the MBLT VmeRead( ). There is a
delay of just over 250uS before the actual MBLT indicated by the burst of
activity on the DTACK.
For our system this delay must be much less than 50uS
in fact probably a maximum of 10uS, ideally less than 1uS i.e. No Delay.
Once the MBLT begins it is very good and fast but this start delay is killing
our system, since it produces data every 100uS which has to be read and
processed in that time.
Problem 2. The MBLT read is not always
continuous
Working through the logic analyser output (MBLT Timing
Diagram 02 - AS Relinquish.jpg) about 10-20% of the time part way through the
MBLT Transfer relinquishes the bus (i.e. AS goes high) momentarily
(typically for 1 to 10uS) before taking back control and completing the
MBLT. This again completely throws our system as the hardware uses the
rising edge of AS to load the next data, so part way relinquish gets a half
of 2 sets of data.
|
Attachment:
MBLT timing diagram 01 - Start Delay.jpg
Description: JPEG image
Attachment:
MBLT timing diagram 02 - AS Relinguish.jpg
Description: JPEG image