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| <== Date ==> | <== Thread ==> |
|---|
| Subject: | RE: Gated ADC |
| From: | "Kalantari Babak" <[email protected]> |
| To: | "Leicester, PJ (Pete)" <[email protected]> |
| Cc: | [email protected] |
| Date: | Tue, 5 Aug 2008 12:49:06 +0200 |
|
Hi Pete, I think 8401 Hytec IP module together with
8002 or 8004 (supports BLT as well) carrier is what you are looking for. Take a
look at http://www.hytec-electronics.co.uk/8401UTM_ISS12.pdf
It has all the features you mentioned. I
would use the INHIBIT input as the hardware gate. If the inhibit input is taken
low the memory update is stopped and an interrupt is invoked (if enabled). We have a driver for waveform but it may require
very little modification only in the interrupt service routine to properly handle
memory inhibit interrupts. Let me know if you need the driver. Regards, Babak From: [email protected]
[mailto:[email protected]] On
Behalf Of Leicester, PJ (Pete) 1) Data collection controlled by a hardware gate signal such
that data is collected into a buffer when the gate is enabled and when the gate
is disabled an interrupt is generated so the data can be transferred into an
I/O Intr processed waveform (or similar) record. 2) Sample rate up to at the least 10KHz but preferably
100KHz, and an absolute minimum of 16 bit. 3) Epics support for waveform record (or MCA or similar). 4) Preferably packaged as an IP module but a VME card
would be OK. Note that the essential feature is the gating of collection
on the hardware signal. We do not want to trigger and collect a fixed number of
samples (most ADC's do this). Any suggestions would be gratefully received. |