Re: Linux DMA driver and device support for Xilinx FPGA

["Cobb, Tom \(DLSLtd,RAL,LSCI\) via Tech-talk" <tech-talk@aps.anl.gov>]

Hi Kiman,

Just a clarification on PandA, it does indeed have its own kernel driver but I didn't write it. The VHDL side was written by Isa Uzun (no longer at Diamond), and the kernel driver was written by Michael Abbott (copied).  The DMA engine is a special streaming engine built into the firmware.

Thanks,

Tom

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From: Tech-talk <tech-talk-bounces@aps.anl.gov> on behalf of Mooney, Tim M. via Tech-talk <tech-talk@aps.anl.gov>
Sent: 09 November 2019 23:30
To: tech-talk@aps.anl.gov <tech-talk@aps.anl.gov>; Ha, Kiman <kha@bnl.gov>
Subject: Re: Linux DMA driver and device support for Xilinx FPGA

 

Hi Kiman,

softGlueZynq uses a DMA component in the FPGA with a PetaLinux kernel driver from Xilinx, and a kernal-to-user-space driver written by a Xilinx engineer, though not supplied with PetaLinux.  It won't do the transfer rate you describe, however.  The estimate I recall was around 240 MB/s to kernel space, and around 130 MB/s to user space.  In softGlueZynq, the DMA transfer is initiated by an aSub record which also stores the data.  Everything - FPGA content, PetaLinux config and code, and EPICS code - is here: https://github.com/epics-modules/softGlueZynq

As you know, the PandaBox also does DMA with the Zynq.  I don't know the details, except that Tom Cobb wrote his own kernel driver.

I think both your and our detector groups are getting higher data-transfer speeds using transceivers.

Tim Mooney (mooney@anl.gov) (630)252-5417
Beamline Controls Group (www.aps.anl.gov)
Advanced Photon Source, Argonne National Lab

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From: Tech-talk <tech-talk-bounces@aps.anl.gov> on behalf of Ha, Kiman via Tech-talk <tech-talk@aps.anl.gov>
Sent: Saturday, November 9, 2019 4:22 PM
To: tech-talk@aps.anl.gov <tech-talk@aps.anl.gov>
Subject: Linux DMA driver and device support for Xilinx FPGA

 

Hello,

 

I am looking for the DMA driver and epics device support module for the Xilinx Zynq and Zynq ultrascal+ core.

Does anyone have to experience generic DMA support for the  Xilinx Zynq or Zynq ultrascal+ core or have a plan for the development?

 

For example, we developed four channel 500 MHz digitizer for the bunch by bunch beam position monitor (performance looks good, < 300 nm turn by tune position for the NSLS-II).

Currently, prototype supports an FPGA logic block ram (BRAM, 8 K/16 K * 16bit * 4, 500MHz clock rate) .

I have plan provides at least 1 M * 16bit * 4)  or 2 M points from the external DDR3/4 memory (FPGA side we implemented DMA core, but Linux part needs help) .

Because our physics group wants to minimum 1000 turns BxB position data.

If we have an epics device support, that’s very valuable for many diagnostics applications, especially beam diagnostics and physics applications.

 

Thanks,

Kiman

 

 

 

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