VMIC 2120 Support

[Graham Waters <waters@Triumf.CA>]

I'm writing device support for the VMIC 2120. This is a 64 bit digital
output device. Its data address map is as follows:

Relative Address	mnemonic	function

xxx0			DR0		data register 0 (bits 56 - 63)
xxx1			DR1		data register 1 (bits 48 - 55)
xxx2			DR2		data register 2 (bits 40 - 47)
xxx3			DR3		data register 3 (bits 32 - 39)
xxx4			DR4		data register 4 (bits 24 - 31)
xxx5			DR5		data register 5 (bits 16 - 23)
xxx6			DR6		data register 6 (bits  8 - 15)
xxx7			DR7		data register 7 (bits  0 - 7)

For binary output support I use a 32 bit write to DR0 or DR4 in the
following
manner:

	if (signal > 31) use DR0
	else use DR4

A problem arises with mbbo support. At the record support level
the value field is set to zero for signals > 31.

I've looked at several options:

1) Regard the module as two separate 32-bit devices with different base
addresses
2) Use PARAM as an address offset (eg #C0 S0 @0x0004 or #C0 S0 @0x0000)
3) bypass the VAL field and access the the state masks directly

I'm sure this problem will crop up with other devices.
Anyone have any suggestions

Graham.

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| Graham Waters, Control System Eng          Internet: waters@triumf.ca
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| TRIUMF --- University of British Columbia,	phone: (604)-222-1047   |
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