Experimental Physics and Industrial Control System
Peter Denison gave me the following link to the Linux kernel sources
which gives a reasonable description of sync, lwsync, eieio and wmb, rmb
etc.
http://lxr.linux.no/source/include/asm-ppc64/system.h#L18
I assume that at the bottom of cacheFlush and cacheInvalidate is a sync
instruction on the PPC, but I might be wrong. I certainly don't see it.
The problem we have found with the 5500 is, I think, related to the
problem outlined in the 2002 tech-talk thread. The processor MMU may
know the VME memory isn't cached, but there is also a cache in the VME
chip (why, I don't know) and that has to be forced as well.
Cheers,
Nick Rees
Principal Software Engineer Phone: +44 (0)1235-778430
Diamond Light Source Fax: +44 (0)1235-446713
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