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<== Date ==> | <== Thread ==> |
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Subject: | VME Bus Error handling on MVME3100 and 6100 boards |
From: | Andrew Johnson <[email protected]> |
To: | EPICS tech-talk <[email protected]> |
Date: | Thu, 10 Aug 2006 12:24:06 -0500 |
2.3.5 VMEbus Exception Handling
When a VMEbus transfer initiated by the VME Master does not complete successfully, the status is saved in the VMEbus exception registers. The exception registers are updated when a transaction is terminated with a bus error, or a 2eVME or 2eSST transfer is terminated with a slave termination.
When the VME Master encounters one of these conditions, any write data in the buffers is removed (flushed). If the transaction was a VMEbus read, the VME Master completes the Linkage Module command by filling the buffer with a data pattern of all ones.
Tip: The interrupt controller can be programmed to generate an interrupt when the exception registers are updated.
The Tsi148 PCI Target never terminates a transaction with a Target-abort
SIGTA (Signalled Target Abort): The Tsi148 does not generate a target abort, therefore this bit is hard-wired to a logic 0.
- Andrew -- Not everything that can be counted counts, and not everything that counts can be counted. -- Albert Einstein