Re: VME Bus Error handling on MVME3100 and MVME6100 boards

[Andrew Johnson <anj@aps.anl.gov>]

Kate Feng wrote:
> Andrew Johnson wrote about mvme6100:
>
> > The only sure-fire way around this problem is to check
> > the Tempe chip's VMEbus Exception Attributes Register after every
> > write operation and every read that returns an all-1s bit pattern
>
> This can be implemented at the level of the Tsi148 driver
> instead of the EPICS driver, right ?

All the EPICS VME drivers that I know assume that they have memory 
mapped I/O to the VME card and thus do not make an OS or BSP call to 
perform read or write cycles on the VME bus.  If they *did* call an OS 
or BSP routine then it would be possible for a Tsi148 driver to 
intercept all such I/O operations and perform the necessary checks 
afterwards.  However since they don't (most EPICS drivers create a 
struct that directly maps to the board registers and use a pointer to 
that struct to calculate the register address) the above requirement 
would need major changes to every driver to properly handle the issue of 
getting a bus error.

This doesn't mean that the existing drivers won't work; the vast 
majority of the time they will be fine.  They will not be robust in the 
presence of unexpected bus errors though.

> > - clearly not something conducive to good I/O
> > performance, and not compatible with any existing EPICS drivers.
>
> At least, only the VME devices implemented with the 2eSST protocols
> are eight times faster than the regular one, which somehow compensate
> the overhead. The only possible performance gain over the Universe
> on the VME backplane lies at the MBLT  via the DMAs of the tempo chip
> using the 2eSST protocols, which will be confirmed by Timo.

2eSST is not relevent to the programmed I/O operations I was talking 
about above.  The issue of bus errors occurring during a DMA transfer 
are dealt with using a different mechanism which should be fine on the 
Tempe chip.

- Andrew
--
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