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<== Date ==> | <== Thread ==> |
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Subject: | Re: CSR/CR questions |
From: | "Bjorklund, Eric A" <[email protected]> |
To: | Bai Jiaoni <[email protected]> |
Cc: | "<[email protected]>" <[email protected]> |
Date: | Mon, 29 Oct 2012 23:33:04 +0000 |
On Oct 29, 2012, at 1:55 AM, Bai Jiaoni wrote:
1 Why one CSR/CR has 8 ADER instead of only one?
On one level, this is a hard question to answer because I don't completely understand your WriteToVme8 routine. I assume that VCSR is the cpu address of the start of CR/CSR space. Shifting nGeo (which I assume is the slot number?) back and forth by 4
bits puzzles me. However, assuming that is what you intended to do, I think I do see one problem. Your second call to WriteToVme8 writes nGeo>>4 (which would be 0 if nGeo is 6) to 7ffdf -- which is the byte where the address mode should be written on ADER
7. The byte addresses for ADER 7 (if I've done the addition correctly) should be:
7ffd3: High order byte of the VME base address
7ffd7: 2nd highest order byte of the VME base address
7ffdb: 3rd highest order byte of the VME base address
7ffdf: VME Address mode (shifted left 2 bits)
On another level, however, the question is much easier. Since you are using EPICS, just call the CSRSetBase routine from the devlib2 library.
If you don't have the devlib2 library already, you can get it at:
The following code can be used to set the base address (in ADER 7) of the module in slot 6 to 0x40000 in A24 space:
/* Make sure Slot 6 has a CR/CSR enabled card in it (if so, returns base CR/CSR address for slot 6) */
volatile unsigned char* slotBase = devCSRProbeSlot(6);
/* Set the base address to 0x40000 (A24) */
if (!slotBase)
CSRSetBase(slotBase, 7, 0x40000, VME_AM_STD_SUP_DATA);
Hope this is helpful.
-Eric Bj.
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