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<== Date ==> | <== Thread ==> |
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Subject: | Re: IOC Crash with No Exception Generated |
From: | Ricardo Cardenes via Tech-talk <[email protected]> |
To: | [email protected] |
Cc: | Talk EPICS Tech <[email protected]> |
Date: | Thu, 26 Jul 2018 09:16:06 -1000 |
Hi Matt,
On 07/25/2018 08:52 PM, Matt Rippa via Tech-talk wrote:
> Is there a way to force an exception (or stack trace), for example with
> watchdog?
>
> RTEMS 4.10.2/EPICS 3.14.12.7 MVME2307 BSP
Back in 2000 we were having this kind of issue on some of our VxWorks
systems, and I wrote some code for a couple of different CPU boards
(MVME167 and 172) which connected an interrupt handler to the Abort
button interrupt. When the button was pressed this routine dumped the
status of a selected set of tasks into an area of memory that was
configured to survive a reboot, allowing us to show that status after
bringing the system back up.
My code would be no use to you on a different CPU board and OS, but the
idea of connecting something up to an Abort button interrupt if your
boards have one might help. You'll need the hardware manual for the CPU
board to work out how to enable and connect the abort interrupt, but
most Motorola/Emerson/Whoever boards do have such a button.
I will add that the PowerPC CPUs seem to be a bit more prone to the CPU
completely hanging up than the 68Ks were, which I think tends to happen
if they get a Bus Error (PCIbus Target Abort) from code running inside
an interrupt handler/ISR. If you have any ISRs that do VMEbus I/O you
might want to look at whether they can be converted into high priority
threads that sit waiting on a semaphore, and have the ISR do nothing but
trigger that semaphore. This will increase the interrupt latency and
jitter, but would prevent hangups if something goes wrong with the VME I/O.
HTH,
- Andrew
--
Arguing for surveillance because you have nothing to hide is no
different than making the claim, "I don't care about freedom of
speech because I have nothing to say." -- Edward Snowdon