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<== Date ==> | <== Thread ==> |
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Subject: | Re: MVME3100 boot failure at "Trying to find CSR on VME" |
From: | "Johnson, Andrew N. via Tech-talk" <tech-talk at aps.anl.gov> |
To: | Peter Linardakis <peter.linardakis at anu.edu.au> |
Cc: | EPICS tech-talk <tech-talk at aps.anl.gov> |
Date: | Tue, 30 Nov 2021 15:05:43 +0000 |
On Nov 29, 2021, at 8:33 PM, Michael Davidsaver via Tech-talk <tech-talk at aps.anl.gov> wrote:
Since the CPU on this backplane apparently hangs before printing that “CRG” message, my guess is that either the VME system controller isn’t generating a BERR signal if/when nothing responds to the I/O cycle after some suitable timeout interval
(I assume from the probe operation in the call at line 1717), or maybe that the backplane has a problem with its BERR* signal line not working properly (is it terminated properly?). If the CPU doesn’t see a falling edge on either the BERR or DTACK signal it
will hang waiting for a data from the read cycle which never completes. If this CPU *is* the VME system controller the code should have enabled a cycle timeout, but going back to what Heinz was talking about you need to make sure that the SCON is properly
enabled and that the CPU is in slot 0.
- Andrew
--
Complexity comes for free, simplicity you have to work for.
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