Hello,
Just so you you can be informed about basic information about
my system:
- I am using EPICS version 3.15.5
- My board has an FPGA ZYNQMP UltraScale
- I am using Buildroot 2019.02.9 to generate my OS image
I have encountered the next issue:
PVs that you read from the FPGA get "frozen" if the EPICS driver is
started before the NTP Synchronization is done. Is this just a
coincidence? Am I missing something about these PVs? Is there really
a relationship between system time and the correct functioning of
the IOC? If not, what could be freezing the PVs.
I have temporarily solved this by just waiting for the NTP to get
synchronized so that the System Date is corrected, but I wish I
could just start it and "unfreeze" those PVs. Is there any kind of
way I can make the channel access independent from any given time?
Thanks a lot in advance,
Pepe.
