Re: Read and Write errors with VME-EVR-300

[Heinz Junkes via Tech-talk <tech-talk at aps.anl.gov>]

I'm getting a little puzzled now.

I had similar problems with the interrupt vector on the VMEBus with the VMEbus board from Struck (SIS3316).
I could prove with a VMEbus bus analyzer (VMEtro) that Struck does not leave the vector on the bus long enough.
This was then fixed by Struck by adapting their VME-FPGA programming.
If I understood correctly, they use a Xilinx Spartan 6 FPGA for the VMEbus control.
With faulty register reading I had the same assumption that the timing of the FPGA is not kept 
properly (this could have something to do with the clock frequency of the FPGA). 

But here we didn't really come to a solution and to be able to put the system into use I found by chance 
the the 2 CPU solution and use it since then.

Do the EVM and EVR boards also use FPGA's for the VMEbus?

Heinz


> On 5. Oct 2022, at 04:38, Hong, Ran <rhong at anl.gov> wrote:
> 
> Dear Heinz,
> 
> I tried the 2-CPU scheme and it seems working. I have mvme3100 as the arbiter and mvme2500 as the CPU for the IOC. I will investigate a few other places of the code and see if this problem goes away. Particularly, I will check the ISR function. I had interrupt problems before. If I had more than 1 EVR in the crate, it had interrupt errors. I solved this problem by adding a read-back in the ISR function, but I had no idea why that could work. 
> 
> Ran Hong
> 
> From: Heinz Junkes <junkes at fhi-berlin.mpg.de>
> Sent: Tuesday, October 4, 2022 6:34 AM
> To: Hong, Ran <rhong at anl.gov>
> Cc: tech-talk at aps.anl.gov <tech-talk at aps.anl.gov>
> Subject: Re: Read and Write errors with VME-EVR-300
>  
> Hello Ran Hong,
> I have similar problems in a constellation with MVME6100 and STRUCK SIS3316.
> 
> I could solve the problem ( not elegant ) by using another (old) CPU as VME arbiter in slot 1
> and disabling the arbiter on the MVME6100 and plugging the CPU into slot 2.
> Heinz
> 
> 
> > On 4. Oct 2022, at 02:29, Hong, Ran via Tech-talk <tech-talk at aps.anl.gov> wrote:
> > 
> > Hello All,
> > 
> > I am testing a VME IOC with 1 VME-EVM-300 and 6 VME-EVR-300 boards. The CPU board is mvme-3100, and the driver is derived from mrfioc2:
> > https://github.com/epics-modules/mrfioc2
> > I experienced many errors like missing time stamp, incorrect GTX waveform, and so on. They all stem from issues when reading from or writing to VME registries using READ32 or WRITE32 in the driver. For example, in evrMrmApp/src/drvem.cpp line 803 to 806 for latching the timestamp, 
> > epicsUInt32
> >  ctrl=
> > READ32
> > (base,
> >  Control);
> > 
> > 
> > //
> > 
> >  Latch timestamp
> > 
> > WRITE32
> > (base,
> >  Control, ctrl|Control_tsltch);
> > 
> > 
> > It reads the control registry, modify the bit for timestamp latch, and write it back to the control registry. Occasionally, I saw the READ32 returns 0xffffffff, which is an invalid value for the control registry, and the subsequent WRITE32 results in a mess in the EVR.
> > 
> > Has anyone experienced similar issues? Any suggestions to prevent or mitigate the VME I/O errors?
> > 
> > Thanks!
> > 
> > Ran Hong