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| <== Date ==> | <== Thread ==> |
|---|
| Subject: | Re: Read and Write errors with VME-EVR-300 |
| From: | Andrew Johnson via Tech-talk <tech-talk at aps.anl.gov> |
| To: | Michael Davidsaver <mdavidsaver at gmail.com>, "Hong, Ran" <rhong at anl.gov> |
| Cc: | "tech-talk at aps.anl.gov" <tech-talk at aps.anl.gov> |
| Date: | Wed, 5 Oct 2022 11:45:51 -0500 |
On 10/5/22 10:56 AM, Michael Davidsaver via Tech-talk wrote:Talking of seeing a change when a separate card is When we got our first MVME board that used a Tempe (TSI-148) chip we found that unlike the older VMEchip2 and Universe-2 chips the Tempe would not release some of the strobe lines (probably DS*, AS* and/or IACK* but I forget exactly which) at the end of a bus cycle until it needed to run the next bus cycle or to release ownership of the bus. The older VME chips released those/that strobe immediately, whether they had another cycle to run or not. There was no timing requirement from the VMEbus spec that a bus master should do that, but at least one of our older VME I/O boards had problems with that — it might have been that it didn't actually cancel its internal "interrupt pending" state until IACK* got released. IIRC using another board as the system controller made the Tempe release the strobe and its ownership of the bus at the end of the cycle, thus resolving the issue. Not sure if this Tempe behavior could help explain the problem, probably not though... - Andrew -- Complexity comes for free, Simplicity you have to work for. |