Re: Read and Write errors with VME-EVR-300

[Michael Davidsaver via Tech-talk <tech-talk at aps.anl.gov>]

On 10/3/22 17:29, Hong, Ran via Tech-talk wrote:
> Hello All,
>
> I am testing a VME IOC with 1 VME-EVM-300 and 6 VME-EVR-300 boards. The CPU board is mvme-3100, and the driver is derived from mrfioc2:
> https://github.com/epics-modules/mrfioc2 <https://github.com/epics-modules/mrfioc2>
> I experienced many errors like missing time stamp, incorrect GTX waveform, and so on. They all stem from issues when reading from or writing to VME registries using READ32 or WRITE32 in the driver. For example, in evrMrmApp/src/drvem.cpp line 803 to 806 for latching the timestamp,
> epicsUInt32 ctrl=READ32(base, Control);
It should be noted that this is with vxWorks.


> //Latch timestamp
> WRITE32(base, Control, ctrl|Control_tsltch);
>
> It reads the control registry, modify the bit for timestamp latch, and write it back to the control registry. Occasionally, I saw the READ32 returns 0xffffffff, which is an invalid value for the control registry, and the subsequent WRITE32 results in a mess in the EVR.
>
> Has anyone experienced similar issues? Any suggestions to prevent or mitigate the VME I/O errors?
There was an issue with the VME logic which manifest
most often as a bus error when reading this register.
However, this issue was isolated and fix back in Feb.
2011.

Jukka may remember better.  As I recall, the root
cause was a FW issue during the arbitration part
of a VME cycle whereby one MRF card would pull the
bus error line during an operation intended to access
another.  So it only manifest when more than one
MRF card were present.

https://github.com/epics-modules/mrfioc2/blob/a8cb48d549b7aae13206cf2d168c6f1cfec2e1c4/evrMrmApp/src/drvem.cpp#L811-L817

Talking of seeing a change when a separate card is
acting as VME arbiter make me wonder if a similar
sort of issue has arisen.

(software has very little involvement in VME bus