Experimental Physics and Industrial Control System
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On 10/5/22 10:56 AM, Michael Davidsaver via Tech-talk wrote:
Talking
of seeing a change when a separate card is
acting as VME arbiter make me wonder if a similar
sort of issue has arisen.
When we got our first MVME board that used a Tempe (TSI-148) chip we
found that unlike the older VMEchip2 and Universe-2 chips the Tempe
would not release some of the strobe lines (probably DS*, AS* and/or
IACK* but I forget exactly which) at the end of a bus cycle until it
needed to run the next bus cycle or to release ownership of the bus.
The older VME chips released those/that strobe immediately, whether
they had another cycle to run or not. There was no timing
requirement from the VMEbus spec that a bus master should do that,
but at least one of our older VME I/O boards had problems with that
— it might have been that it didn't actually cancel its internal
"interrupt pending" state until IACK* got released. IIRC using
another board as the system controller made the Tempe release the
strobe and its ownership of the bus at the end of the cycle, thus
resolving the issue.
Not sure if this Tempe behavior could help explain the problem,
probably not though...
- Andrew
--
Complexity comes for free, Simplicity you have to work for.
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- References:
- Read and Write errors with VME-EVR-300 Hong, Ran via Tech-talk
- Re: Read and Write errors with VME-EVR-300 Michael Davidsaver via Tech-talk
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ANJ, 05 Oct 2022 |
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