EPICS Home

Experimental Physics and Industrial Control System


 
1994  1995  1996  1997  <19981999  2000  2001  2002  2003  2004  2005  2006  2007  2008  2009  2010  2011  2012  2013  2014  2015  2016  2017  2018  2019  2020  2021  2022  2023  2024  Index 1994  1995  1996  1997  <19981999  2000  2001  2002  2003  2004  2005  2006  2007  2008  2009  2010  2011  2012  2013  2014  2015  2016  2017  2018  2019  2020  2021  2022  2023  2024 
<== Date ==> <== Thread ==>

Subject: FW: Serial Configuration on a Greenspring Octal serial IP
From: [email protected] (Peregrine McGehee)
To: "'[email protected]'" <[email protected]>
Date: Wed, 19 Aug 1998 11:08:50 -0600
The driver mentioned below has a separate routine for setting the port parameters. 
This is, of course, highly specific to the SCC2698 UART.


-----Original Message-----
From:	Peregrine McGehee [SMTP:[email protected]]
Sent:	Wednesday, August 19, 1998 9:35 AM
To:	'[email protected]'
Cc:	'[email protected]'
Subject:	RE: Serial Configuration on a Greenspring Octal serial IP

Arne,

I last worked on this driver in October of last year. It is a vxWorks tyLib() style driver based
on what was done at APS for HiDEOS.

There are some bugs that I will be fixing during the next week which stem from the old
HiDEOS driver. Specifically (from Joe Sullivan at APS):

------------------------------------
The first fix _was_ in the transmit ISR logic. The code was wrong to only
check the status registers's TxRDY bit before executing the TX logic. The
interrupt mask register's (IMR) TxRDY bit needed to be checked also to assure
that a TX request had been made. The SR's TxRDY bit is going to be on
most of the time, whether it caused an interrupt or not. 

HiDEOS code segment...

void* OctualUartTask::ifunc(void *v)
{
.
.
          // a byte needs to be sent
          // if(sr&0x04) - original code. 
          if ((qt->imr[st->block]&st->imr) && (sr&0x04))  
          {
                // Start of TX logic 
.
.
}

Second, interrupts were not being masked out when the IMR's TxRDY bit was
set during the user's WRITE function. That left open a window when the
UART's data structure did not match the state of the chip. 

int OctalUartTask::Write(StringMsg* m)
{
.
.
>>>  lockKey = IntLockGet();    
   quad_table->imr[block]|=imr; // activate Tx interrupt
   regs->u.w.imr=quad_table->imr[block];        // enable Tx interrupt
>>>  IntLockRelease(lockKey);
.
.
}

We also decided it was safer not to output the first character from
the Write function. 
------------------------------


The URL is:
http://www.cfht.hawaii.edu/~tcs/tcsiv/tygsoctal.html

It should work under vxWorks 5.2.

Aloha,
	Peregrine 

Navigate by Date:
Prev: Re: Serial Configuration on a Greenspring Octal serial IP Dave Reid
Next: Re: Serial Configuration on a Greenspring Octal serial IP Maren Purves
Index: 1994  1995  1996  1997  <19981999  2000  2001  2002  2003  2004  2005  2006  2007  2008  2009  2010  2011  2012  2013  2014  2015  2016  2017  2018  2019  2020  2021  2022  2023  2024 
Navigate by Thread:
Prev: Re: Serial Configuration on a Greenspring Octal serial IP Maren Purves
Next: Re: Serial Configuration on a Greenspring Octal serial IP Kay-Uwe Kasemir
Index: 1994  1995  1996  1997  <19981999  2000  2001  2002  2003  2004  2005  2006  2007  2008  2009  2010  2011  2012  2013  2014  2015  2016  2017  2018  2019  2020  2021  2022  2023  2024