Re: mvme5500 (was National Instruments VME-MXI-1 modules vs. modernVMECPU modules)

[Andrew Johnson <anj@aps.anl.gov>]

Kate Feng wrote:
>
> Please do not forget the system controller is in between the CPU and the
> VME slave.

You have either your nomenclature or your understanding of the 
architecture confused.  The Universe-2 is between the CPU and the VME 
slave, but as I explained it can completely decouple the cycles on the two 
busses in some cases, and in others (such as VMEbus IACK cycles) there is 
no equivalent PCIbus cycle going on at all.

> How can the CPU see the DTACK asserted by the slave if the system
> controller is holding it up until the right time ?

The CPU doesn't see DTACK, the Universe-2 chip does, and it doesn't go 
through the system controller (go back and read my last message again, 
where I say CPU I really mean the PowerPC processor chip via its PCI host 
bridge).  In the case of a Read cycle the Universe-2 will read the data 
off the VMEbus and pass it back to the CPU and finish the pending PCIbus 
read cycle.  However for a posted write cycle there is no reason to delay 
the CPU until the write completes, as it may be able to execute tens or 
even hundreds of instructions between performing the PCIbus write cycle 
and the VMEbus cycle completing.

The Universe-2 chip is not a simple VME signal interface like I suspect 
the Motorola VMEchip device was; there really is a lot going on under the 
hood, and it only couples the two busses together (i.e. delays its 
response on one while it's waiting for a related response on the other) if 
they really need to be coupled.  That generally only occurs when the CPU 
does a read from a VMEbus address, or another VMEbus master does a read of 
memory on this card.

- Andrew
--
Dear God, I didn't think orange went with purple until I saw
the sunset you made last night.  That was really cool. - Caro