Andrew Johnson wrote:
> Kate Feng wrote:
> >
> > I thought Tundra Universe-2 chip, who entertains the address
> > pipelining, is just a PCI-VME bridge, not a CPU. The address
> > pipelining you saw on the VME bus should originate from the CPU bus.
> > Otherwise, I imagine it would be a big SW/HW challenge to design a
> > working VME SBC if address pipelining of the VME is not related to
> > that of CPU.
>
> The term "address pipelining" in the context of VMEbus means that the bus
> master is permitted to start placing the address of the next bus cycle on
> the address bus before the data transaction of the previous cycle has
> fully completed - it can release AS* and change the address as soon as it
> sees the slave has asserted DTACK*.
Please do not forget the system controller is in between the CPU and the VME
slave. How can the CPU see the DTACK asserted by the slave if the system
controller is holding it up until the right time ?
Kind regards,
Kate
> The page you found at
> http://www.vita.com/vmefaq/readwritecyc.html explains this in the last
> section.
>
> If you look at the diagram of the Tundra Universe-2 chip at
> http://www.tundra.com/Products/Bridges/UniverseII/index.cfm you'll see
> that it contains 5 different channels which connect the PCIbus and the
> VMEbus in some way. Those channels are mostly autonomous within the chip,
> and it's possible for several of them to be waiting to perform a VMEbus
> cycle at once - in fact the PCI Target Channel contains a FIFO for Posted
> Write cycles, and as a result it can have several write cycles queued up
> and waiting to be executed on the VMEbus. The following is just one
> example of how the Universe-2 can completely decouple a PCIbus cycle from
> the VMEbus cycle, and this example uses just one of the channels (there
> are other scenarios involving more than one channel which can also result
> in VMEbus address pipelining).
>
> A posted write cycle on the PCI Target Channel is one that can complete on
> the PCIbus before the VMEbus cycle even starts - there is no need for the
> main CPU to wait for the VMEbus cycle to complete because it doesn't need
> any information from the transaction to continue on executing its next
> instruction. The PCIbus cycle causes the write address and data to be
> pushed into the FIFO and the PCI cycle immediately completes, irrespective
> of the state of the other end of the FIFO. I forget how long the write
> posting FIFO is, but it can contain several write cycles. The VMEbus end
> of the channel will attempt to perform the VMEbus cycles as fast as it can
> in order to drain the FIFO, and it uses address pipelining to maximize
> that throughput (i.e. reduce the time interval between the VMEbus writes).
>
> - Andrew
> --
> Dear God, I didn't think orange went with purple until I saw
> the sunset you made last night. That was really cool. - Caro
- Replies:
- Re: mvme5500 (was National Instruments VME-MXI-1 modules vs. modernVMECPU modules) Andrew Johnson
- References:
- mvme5500 (was National Instruments VME-MXI-1 modules vs. modern VME CPU modules) Kate Feng
- Re: mvme5500 (was National Instruments VME-MXI-1 modules vs. modern VME CPU modules) Andrew Johnson
- Re: mvme5500 (was National Instruments VME-MXI-1 modules vs. modernVME CPU modules) Kate Feng
- Re: mvme5500 (was National Instruments VME-MXI-1 modules vs. modernVME CPU modules) Andrew Johnson
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