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Subject: | Re: EPICS on FPGA |
From: | "Hill, Jeff via Tech-talk" <tech-talk at aps.anl.gov> |
To: | "tech-talk at aps.anl.gov" <Tech-talk at aps.anl.gov>, Abdalla Ahmad <Abdalla.Ahmad at sesame.org.jo> |
Date: | Wed, 7 Feb 2024 02:14:58 +0000 |
We use Intel FPGA, embed EPICS IOC there as soft core SOC, and use RTEMS for RTOS. Waveforms emitted by algorithm are delivered via DMA to the EPICS IOC memory. We have Lua based subscription update filter selecting beam species flavor. Implemented for BPPMs,
LLRF, and other diagnostic systems. LLRF system is custom boards, but BPPM and others are on COTS VPX FPGA carrier boards. Papers at ICALEPCS.
Jeff
From: Tech-talk <tech-talk-bounces at aps.anl.gov> on behalf of Abdalla Ahmad via Tech-talk <tech-talk at aps.anl.gov>
Sent: Saturday, February 3, 2024 11:34 PM To: tech-talk at aps.anl.gov <Tech-talk at aps.anl.gov> Subject: [EXTERNAL] EPICS on FPGA Hi
I would like to hear about experiences involving installing EPICS on an FPGA, mainly the following: · A brief idea about the control system involved and why an FPGA implementation was better. · What was the hardware platform used? Xilinx, Intel, etc. · What software tools used? Vendor-specific (Xilinx Vivado, Intel Quartus, etc.) or 3rd party tools were used? · What soft processor was used? Or an SoC-FPGA was used?
We have a control system running on an old PowerPC CPU with a deterministic fiber-optic interface and I am researching the idea of implementing it on FPGA.
Thanks for any insight.
Best Regards, Abdalla Al-Dalleh Control Engineer SESAME (Synchrotron-light for Experimental Science and Applications in the Middle East) Fax: +96253511423 abdalla.ahmad at sesame.org.jo
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