Experimental Physics and
Industrial Control System
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| <== Date ==> | <== Thread ==> |
|---|
| Subject: | Re: EPICS on FPGA |
| From: | "Siddons, David via Tech-talk" <tech-talk at aps.anl.gov> |
| To: | "tech-talk at aps.anl.gov" <Tech-talk at aps.anl.gov>, Abdalla Ahmad <Abdalla.Ahmad at sesame.org.jo>, "Mooney, Tim M." <mooney at anl.gov>, "Cobb, Tom (DLSLtd,RAL,LSCI)" <tom.cobb at diamond.ac.uk> |
| Date: | Tue, 6 Feb 2024 15:53:09 +0000 |
|
Hi Abdalla,
We have been using Zynqs (Microzed, Picozed and a custom board) for several years now to interface our in-house detector systems. We use the FPGA fabric for time-critical interactions with custom ASICs, and the Arm to implement EPICS. We run Debian on the
Arm, so we have access to all of it's capabilities. We build the applications natively on the processor system. We also have implemented a fabric-only UDP system, so we can stream out high-speed data independently of the processor.
Pete.
From: Tech-talk <tech-talk-bounces at aps.anl.gov> on behalf of Cobb, Tom (DLSLtd,RAL,LSCI) via Tech-talk <tech-talk at aps.anl.gov>
Sent: Tuesday, February 6, 2024 7:12 AM To: tech-talk at aps.anl.gov <Tech-talk at aps.anl.gov>; Abdalla Ahmad <Abdalla.Ahmad at sesame.org.jo>; Mooney, Tim M. <mooney at anl.gov> Subject: Re: EPICS on FPGA
Hi Abdalla,
As Tim mentioned, PandABox has a similar approach of running FPGA code and a server on a Xilinx Zynq, but we decided against putting EPICS on the Zynq chip itself. This was because it is a collaboration with SOLEIL who run Tango, so we needed an intermediate
server layer anyway, and also because we wanted to do HDF writing, which is better done on a separate PC. The architecture we now have is a TCP server that runs on the box and does the translation of registers to sensible names and data streaming, then EPICS
or Tango servers which run on a separate PC and talk to that server:
The reasons for using an FPGA over a processor was to do encoder capture and trigger pulse generation
with low and deterministic latency. We use the Xilinx tools (Vivado and the Xilinx provided kernel), and run the server process on the ARM core in a busybox-based Linux distribution.
Thanks,
Tom
From: Tech-talk <tech-talk-bounces at aps.anl.gov> on behalf of Mooney, Tim M. via Tech-talk <tech-talk at aps.anl.gov>
Sent: 04 February 2024 14:30 To: tech-talk at aps.anl.gov <Tech-talk at aps.anl.gov>; Abdalla Ahmad <Abdalla.Ahmad at sesame.org.jo> Subject: Re: EPICS on FPGA
Hi Abdalla,
We haven't installed EPICS actually on an FPGA, but rather alongside an FPGA. We needed simple custom electronics for things like tracking encoders and generating triggers as a function of encoder positions, and we wanted close coordination between the FPGA
stuff and EPICS. We use the Xilinx Zynq chip, in the form of the MicroZed. The tools are Xilinx Vivado, PetaLinux, and High Level Synthesis. The processor is a two-core ARM processor on the Zynq chip, which has good links to the FPGA.
The system is further described here
https://epics-modules.github.io/softGlueZynq/softGlueZynqDoc.html and here
Tom Cobb and others have done something sort of similar at Diamond, yielding the PandAbox
https://quantumdetectors.com/products/pandabox/
which also uses a Zynq chip.
Tim Mooney (mooney at anl.gov) (630)252-5417
Beamline Controls Group (http://www.aps.anl.gov) Advanced Photon Source, Argonne National Lab From: Tech-talk <tech-talk-bounces at aps.anl.gov> on behalf of Abdalla Ahmad via Tech-talk <tech-talk at aps.anl.gov>
Sent: Sunday, February 4, 2024 12:34 AM To: tech-talk at aps.anl.gov <Tech-talk at aps.anl.gov> Subject: EPICS on FPGA Hi
I would like to hear about experiences involving installing EPICS on an FPGA, mainly the following: · A brief idea about the control system involved and why an FPGA implementation was better. · What was the hardware platform used? Xilinx, Intel, etc. · What software tools used? Vendor-specific (Xilinx Vivado, Intel Quartus, etc.) or 3rd party tools were used? · What soft processor was used? Or an SoC-FPGA was used?
We have a control system running on an old PowerPC CPU with a deterministic fiber-optic interface and I am researching the idea of implementing it on FPGA.
Thanks for any insight.
Best Regards, Abdalla Al-Dalleh Control Engineer SESAME (Synchrotron-light for Experimental Science and Applications in the Middle East) Fax: +96253511423 abdalla.ahmad at sesame.org.jo
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- References:
- EPICS on FPGA Abdalla Ahmad via Tech-talk
- Re: EPICS on FPGA Mooney, Tim M. via Tech-talk
- Re: EPICS on FPGA Cobb, Tom (DLSLtd,RAL,LSCI) via Tech-talk
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