Event triggers for plusers not detected (mrf-timing system)

[Karim Laihem <karim.laihem@helmholtz-berlin.de>]

Dear MRF-timing-system community.

Sorry for this long post but sometime details are important.

We have got recently the new VME-EVM-300 and VME-EVR-300. A learning  phase exploring the mrf-timing-system has tarted. So my setup is very simple.
We have achieved some steps in understanding the architecture but still we are facing some questions mainly on the pulse generator triggered on events, pulse delays, fine delays and widths (most important features).

Up to now What I have achieved ?:

• We did manage to cross-compile the driver (mrfioc2-master using devlib2-master) with EPICS-BASE/R3-14-12-5  and RTEMS-Beatnik for MVME-5500.
• We did manage to load the generated binary "rtems-Beatbik" to our MVME-5500.
• As a cross-check before loading the startup script for setting EVG0 and EVR0, we did manage to identify both modules with : "vmecsrdump()" (good sign !)
• We did manage to load the startup-script (settings) for both modules with "mrmEvgSetupVME("EVG0", 2, 0x0, 0x2, 0x1)" and "mrmEvrSetupVME("EVR0", 3 , 0x20000000, 0x5, 0x26)"
  • The loaded settings for EVG0 was without any erros.
  • The loaded settings for EVR0 has shown some errors accessing the VME-base-A32-address (0x3000000). I have used 0x20000000 (indicated by the boot of the MVME-5500). Now no error is shown.
    

Some learning exercises/Tutorials (from PSI docs)  with simple "caget" and "caput" command lines:
We did these exercises using :

• Fractional synthesizer: EVG0 and EVR0 have locked properly (visual check on LEDs (SFPs) and calling some Read-Back status).
• External RF 500 MHz sine, Diver 4 to end-up with 125 MHz event-clock (8 ns clock cycle). EVG0 and EVR0 have locked properly (visual check on LEDs and calling some Read-Back status).
• External RF1300 MHz sine, Diver 26 to end-up with 50 MHz event clock (20 ns clock cycle). EVG0 and EVR0 have locked properly (visual check on LEDs and calling some Read-Back status).

Tutorials with simple "caget" and "caput":
Flowing the tutorials which came with docs (mrfioc2-master) we have achieved the following:

• We did manage to run any EVR0 prescalers and map them to any front panel output FontUnivout(0-5): All outputs work fine (visual check on scope).
• We did manage to run CLM clocks and map them to any FontUnivout(6-7) TTL outputs and to any Diff-outputs (CML0 and CML1) (visual check on scope)

However pulse generators triggered on events reception is still not achieved:

• In this exercise I generate a new record "Pul3-Evt-Trig0-SP" and set it for "event4" as indicated in the document (page 6).
• I didn't manage to generate pulses triggered by event 4 as indicated in the tutorial (page 6).
• In this exercise I generate a special record "Evtmap-1-DNC" to check if LED blinks on reception of "event4" : NO LED BLINKING, NO PULSE
  
• I did change the VAL of the "EvtCode" for the record "TrigEvt4-EvtCode-SP" in the range "0-4" : NO LED BLINKING, NO PULSE.
  

All what I can see on the scope is that the pulser-3 level changes Low and high (horizontal line) when I play on its polarity settings (0 and 1). This is a sign that I'm talking to the right pulser (3) on the right front-pannel-output. But unfortunately no pulsing  is seen yet.

Our conclusion:

• The EVR0 / pulser-3 (all pulsers) do not detect events to be triggered.
• It could be that I'm wrongly configuring the EVG0 and EVR0 in this exercise.
• It could be that I'm missing something very simple and trivial but I cannot see it immediately.

From your experience on the mrf-system I would be very thankful for some support and help to generate pluses with standard delays, with fine delays and widths.

Bellow I did copy and past the out-display from my simple script for this exercise and for its debugging. (maybe it can help to identify the problem)
(if colors are displayed)
Blue color is all what I think to be relevant for locking between EVG0 and EVR0 and some DlyCompensation tests.
Red color is all what I think to be relevant for pulser-3 exercise (Pul3 and event4)

Thanks a lot in advance for your support !
If you have any further question please don't hesitate.

With my best regards.
Karim.
 

***************************************************
Simple setup.
***************************************************

VME64x
PowerPC MVME-5500                           : Slot 1
EVG0                                                    : Slot 2
EVR0                                                    : Slot 3
Driver and libraries : mrfioc2-master, devlib2-master : from "mdavidsaver" and "babak PSI"

***************************************************
    Now check status link between EVG0 and EVR0     
***************************************************
***************************************************
    Now EVG0      
***************************************************

mrf-TEST-EVG0:Enable-RB        Enabled
mrf-TEST-EVG0:DlyCompensation-Beacon-RB Enabled
mrf-TEST-EVG0:DlyCompensation-Master-RB Enabled
mrf-TEST-EVG0:EvtClk-Source-RB External
mrf-TEST-EVG0:EvtClk-RFFreq-RB 1300
mrf-TEST-EVG0:EvtClk-RFDiv-RB  26
mrf-TEST-EVG0:EvtClk-Frequency-RB 50
mrf-TEST-EVG0:EvtClk-PLL-Sts   Locked
mrf-TEST-EVG0:EvtClk-PLL-Bandwidth-RB ML
mrf-TEST-EVG0:SFP1-Speed-Link-I 4300
mrf-TEST-EVG0:SFP1-Status-I    16
mrf-TEST-EVG0:SFP1-T-I         31.1523
mrf-TEST-EVG0:SFP1-Pwr-TX-I    298.9
mrf-TEST-EVG0:SFP1-Pwr-RX-I    259
mrf-TEST-EVG0:SFP1-PowerVCC-I  3.3234
mrf-TEST-EVG0:SFP1-Speed-Link-I 4300
mrf-TEST-EVG0:SFP1-Vendor-I    AVAGO          
mrf-TEST-EVG0:SFP1-Part-I      AFBR-57R5APZ   
mrf-TEST-EVG0:SFP1-Rev-I          
mrf-TEST-EVG0:SFP1-Serial-I    A906420YWU     
mrf-TEST-EVG0:SFP1-Date-Manu-I 2006/10

***************************************************
    Now check with Read-Back EVG0 Trigger Event 4     
***************************************************

mrf-TEST-EVG0:TrigEvt4-Enable-RB Enabled
mrf-TEST-EVG0:TrigEvt4-EvtCode-RB 0

***************************************************
    Now EVR0      
***************************************************

mrf-TEST-EVR0:Pos-I            Slot #3
mrf-TEST-EVR0:Ena-Sel          Enabled
mrf-TEST-EVR0:DlyCompensation-Enabled-RB Enabled
mrf-TEST-EVR0:DlyCompensation-Source-I 0
mrf-TEST-EVR0:DlyCompensation-Target-SP 5000
mrf-TEST-EVR0:Cnt-LinkTimo-I   37149
mrf-TEST-EVR0:Link-Sts         OK
mrf-TEST-EVR0:CG-Sts           OK
mrf-TEST-EVR0:Pll-Sts          Lock
mrf-TEST-EVR0:PLL-Bandwidth-RB ML
mrf-TEST-EVR0:Cnt-RxErr-I      2
mrf-TEST-EVR0:Cnt-RxErr-Rate-I 0
mrf-TEST-EVR0:Cnt-RxErr-Last_  2
mrf-TEST-EVR0:Link-Init-FO_    1
mrf-TEST-EVR0:Link-Clk-I       50
mrf-TEST-EVR0:Link-ClkErr-I    0
mrf-TEST-EVR0:Link-ClkPeriod-I 2e-08
mrf-TEST-EVR0:Cnt-FIFOEvt-I    168393994
mrf-TEST-EVR0:Cnt-FIFOLoop-I   157706597
mrf-TEST-EVR0:Cnt-FIFOLoop-I   157706597
mrf-TEST-EVR0:FIFOCap-I        nan
mrf-TEST-EVR0:EvtClkMode-RB    UpStrm FB:same
mrf-TEST-EVR0:HwType-I         2
mrf-TEST-EVR0:Time-Src-Sel     Event clock
mrf-TEST-EVR0:Time-Clock-I     50


********************************************************
    Settings for Pulser 3 in EVR0 (Tutorial Pul3, page 6)      
**********************************************************

Old : mrf-TEST-EVR0:Pul3-Ena-Sel     Enabled
New : mrf-TEST-EVR0:Pul3-Ena-Sel     Enabled
Old : mrf-TEST-EVR0:Pul3-Polarity-Sel Active High
New : mrf-TEST-EVR0:Pul3-Polarity-Sel Active High
Old : mrf-TEST-EVR0:Pul3-Delay-SP    100
New : mrf-TEST-EVR0:Pul3-Delay-SP    100
Old : mrf-TEST-EVR0:Pul3-Width-SP    200
New : mrf-TEST-EVR0:Pul3-Width-SP    200
Old : mrf-TEST-EVR0:FrontUnivOut0-Src-SP 3
New : mrf-TEST-EVR0:FrontUnivOut0-Src-SP 3
Old : mrf-TEST-EVR0:Pul3-Evt-Trig0-SP 4
New : mrf-TEST-EVR0:Pul3-Evt-Trig0-SP 4
Old : mrf-TEST-EVR0:Evtmap-1-DNC     4
New : mrf-TEST-EVR0:Evtmap-1-DNC     4

***************************************************
  Now check with Read-Back from Pulser 3 in EVR0  
***************************************************

mrf-TEST-EVR0:Pul3-Ena-Sel     Enabled
mrf-TEST-EVR0:Pul3-Polarity-Sel Active High
mrf-TEST-EVR0:Pul3-Delay-RB    100
mrf-TEST-EVR0:Pul3-Width-RB    200
mrf-TEST-EVR0:Pul3-Delay-Raw-RB 5000
mrf-TEST-EVR0:Pul3-Width-Raw-RB 10000
mrf-TEST-EVR0:Pul3-Prescaler-RB 1
mrf-TEST-EVR0:Pul3-Res-I       20
mrf-TEST-EVR0:Pul3-Res-FO_     0
mrf-TEST-EVR0:Pul3-Gate-Mask-RB 0
mrf-TEST-EVR0:Pul3-Gate-Enable-SP 0
mrf-TEST-EVR0:Pul3-SetReset-Sel Reset
mrf-TEST-EVR0:Pul3-Out-I       Low
mrf-TEST-EVR0:Pul3-Name-I      Pulser 3

*******************************************
    Now check map to FrontUnivOut0     
*******************************************
mrf-TEST-EVR0:FrontUnivOut0-Src-RB 3

*******************************************
    Now check Pulser 3 Trig on Event 4     
*******************************************
mrf-TEST-EVR0:Pul3-Evt-Trig0-SP 4
mrf-TEST-EVR0:Evtmap-1-DNC     4

-- 
-----------------------------------------------------------------
Dr. Karim Laihem

Helmholtz-Zentrum Berlin BESSY II, Materialien und Energie GmbH
Albert-Einstein-Str. 15, 12489 Berlin

Email.: karim.laihem@helmholtz-berlin.de
Tel.: +49 30 8062 - 15066       Fax.: +49 30 8062 - 14980/14632
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