RE: compact PCI versus VME

["Jeff Hill" <johill@lanl.gov>]

Title: RE: compact PCI versus VME

Ø  what fpga are you using for this?

 

That design uses a 400Mhz XScale microprocessor external to the FPGA.

 

Ø  Are you integrating timing in the compact Rio?

 

Micro Research Finland has a cRIO  timing event receiver design in progress.

Ø  Why use the proprietary backplane in place of just dedicated fast serial interfaces?

Personally, I am not enamored of proprietary backplanes, nor wire nanny-nudging proprietary programming languages with binary source code formats changing every release,  but the idea of modular analog front-ins that attach directly to the pins of the FPGA is a pretty good one. With the cRIO approach for example the wire scanner DAQ and stepper motor control logic IP can be in the same FPGA. The downside is that DAQ BW appears to be limited based on the number of FPGA pins allocated to each of the signal conditioning modules.

 

Jeff
______________________________________________________
Jeffrey O. Hill           Email        johill@lanl.gov
LANL MS H820              Voice        505 665 1831
Los Alamos NM 87545 USA   FAX          505 665 5107

 

Message content: TSPA

 

From: Dalesio, Leo [mailto:dalesio@bnl.gov]
Sent: Tuesday, January 26, 2010 2:01 PM
To: Jeff Hill; Hoff, Lawrence
Cc: Fred E. Shelley Jr.; Eric Bjorklund; tech-talk@aps.anl.gov
Subject: RE: compact PCI versus VME

 

 

For LANSCE LLRF they need the real-estate provided by 6u boards, and for DAQ
the bandwidth between the FPGA and the analog modules isn't appearing to be
sufficient in cRIO. So for those systems we need either cPCI, VME, or uTCA.
If we have a centralized CPU then the bandwidth in cPCI Express, VME/VXS, or
uTCA for DAQ interconnects looks attractive. Another option which we are
looking at is to just run EPICS embedded on every one of the (Ethernet
directly connected) DAQ/LLRF modules thereby eliminating the system
interconnect as a bottleneck/complexity between the DAQ/FPGA hardware and
switched Ethernet.
----------what fpga are you using for this? We looked at putting a power PC core onto the FPGA, then we found out that this would not be supported on their next generation FPGA. We have been looking at running the micro blaze processor on it - and using a canned modbus server to talk to it over a 1Git Ethernet port.

Are you integrating timing in the compact Rio?
Why use the proprietary backplane in place of just dedicated fast serial interfaces?