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Subject: SIS3820 scaler limits
From: Mark Davis <davism50@msu.edu>
To: "tech-talk@aps.anl.gov" <tech-talk@aps.anl.gov>
Date: Fri, 29 Mar 2013 15:57:34 -0400
I am new to synApps and use of scaler/counters, etc. and I have some questions regarding the use and capabilities of the SIS3820 VME scaler and its driver.

Our current setup for the project I am working on is a VME crate with an Emerson MVME3100 CPU board, an SIS3820 scaler, and a Hytec VDD2670 DAC.  Don't know at the moment how much memory the CPU card has, or if the memory card on the 3820 is larger than 64M.  The CPU is running RTEMS rather than VxWorks.

The use of this setup is currently a fairly straightforward scan (using sscan records) where the DAC output is ramped over a range of values, and a new count captured at the end of each acquisition period (dwell time) during which the DAC output is stable.  The dwell time is currently hundreds of milliseconds, so nothing that even comes close to the limits of the scaler card.

But the next step is to support the following scenario:
  • An external pulse indicates when to start counting the number of events on a single channel.  This pulse will repeat about every 10ms (100 Hz)

  • For each external pulse, begin counting event pulses on the one channel.  At regular intervals, capture the current counter value (doesn't matter if it is reset at the start of each period, although I am guessing that NOT resetting it is probably safer, as it would be less likely to miss an event close to the start of the next interval).

  • Continue this for a specified number of the regular intervals, then stop capturing the counter value until the next external pulse

Basically there will be an external pulse once every 10ms that indicates the start of a 1ms long period of interest.  During that 1ms period, we need to capture the state of the counter as often as possible (minimum dwell time), but at regular intervals.

The original specs called for the dwell time to be 20ns, but after looking over the specs on the 3820, it seems that is not possible.

So here are my questions:
  • What IS the minimum dwell time for counting on a single channel?  The smallest one indicated in the documentation says 220ns for 8 channels (using 8-bit counts, which - as the doco points out - is more than large enough for such short dwell times).  Can this be made even smaller when we really only need to count 1 channel?  Or maybe 2, if we needed to also count 50MHz pulses on channel 1 to use as a time reference?

  • The minimum dwell times for the "Histogramming Scaler mode (MCS with add enabled)" are longer than those for the MCS mode with the same number of channels and counter depth.  Why is that?  Is it really doing an addition operation that is taking up time?  I would have thought that the Histogram mode would be the same as the MCS mode except that you do NOT take the time to clear the counts (expect prior to the first scan).  And to guard against incrementing the counts between scans, simply disabling the inputs or counting of them would do the job.  So unless disabling the counting between scans takes a lot longer than clearing them at the start of each scan, I would think that the Histogram mode would have the same or shorter dwell times than MCS mode, not LONGER!  Why is it the other way around?

  • Is it possible to get at least the 220ns dwell time performance using the existing driver, or would I have to modify it? 

  • If modification is not needed, how do I get it do do the MCS mode with 8-bit counts and the 220ns dwell time?

  • If I modified the driver, could I get even smaller dwell times (without changing the firmware/FPGA programming)?

  • Can someone explain the LNE (Load Next Event) concept?  Depending the context it is used in, it seems that sometimes it means to advance which channel's count is being incremented, and other times it seems to mean copy the counts to the FIFO.  Is either of these correct?  Does it mean something different for different modes?  When does it apply and when does it not?


Probably more questions as I dig in to this some more, but any pointers, explanations, insights, suggestions, etc  would be much appreciated.

Thanks,

Mark Davis
NSCL, MIchigan State University


Replies:
RE: SIS3820 scaler limits Mark Rivers
RE: SIS3820 scaler limits Mark Rivers

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