Strange Behavior on 33Mhz MV167 boards

["Eric Bjorklund, NPSM" <BJO@accr.lcs.lanl.gov>]

Hi all,

We have encountered a rather puzzling anomaly on our 33Mhz MV167 boards that
does not appear in the 25Mhz version. A busy-loop waiting for a hardware
register to clear in A32 space fails on our 33Mhz MV167 boards, but works on
our 25Mhz boards. (a quasi-random sampling (2 boards) of our 33 Mhz boards
was able to reproduce the problem 100% of the time).

At first inspection it appeared like we might be having a caching problem,
since the 25Mhz CPUs took about 300 iterations before the register cleared, and
the 33Mhz CPUs took anywhere between 300 and 84000 iterations, and sometimes
didn't even clear after 100000 iterations (obviously this is not scaling up by
the expected 32% based on the faster cpu).  The problems with this theory,
however are:

 1) The A32 address space (0x80000000 on up) has data caching disabled via
    the DTT1 register (JRW_RAM_HACK in sysALib.s and usrConfig.c), and
 2) Disabling all data caching (cacheDisable (1)) did not make the problem
    go away.

What did make the problem go away was disabling *Instruction* caching
(cacheDisable (0)).  So, the current hypothesis is that tight loops (probably
executing entirely within the instruction cache) referencing A32 space do
not reliably get their read references updated on 33Mhz MV167 boards.

If it is any help to understanding the problem, the machine code from the
loop in question follows the form:

	:
	:
	clrl	d1
L104:
	movel	a4@,d0
	jeq	L101
	addql	#1,d1
	cmpl	#100000,d1
	jcs	L104
L101:
	:
	:

In the example above, a4 contains the register address in A32 space and
it is the indirect read through a4 (second instruction) that seems to be
failing.


Has anyone else observed this behaviour and/or have a fix for it?

Eric Bj.


==============================================================================
Eric Bjorklund				Voice: 505-667-6031
Los Alamos National Laboratory		Email: bjorklund@lanl.gov
LANSCE-6 MS H828
PO Box 1663
Los Alamos, NM 87545
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