Hi Emmanuel,
Our boards are not MTCA. They are pizza boxes. (More appropriate for the NY area).
They have two components:
The Digital Front End which has
Xilinz 6
Event Receiver
Optical Redundant IO Network for low latency data comm
4 Ethernet SFPs
4 GB of DDR RAM
IO Connector
Ethernet connection for EPICS
Applications:
BPM: DFE and a BPM Analog Front End
Cell Controller: used to distribute BPMs and perform FOFB at 10 Hz, Sends control points over Ethernet to PSs.
Active Interlock: Cell controller that performs machine protection using 10 kHz machine data
Correlator: detects events at (50? MHz) - no extra IO used
Triggered Position Capture: AFE is a general IO board with 8 encoder mirroring signals
Gerneral Beam line IO: AFE has a set of analog and digital signals that can be captured and time stamped for experiments 8 nsec resolution
LBL is using this platform for their BPMs. THey have a significantly different AFE and they have rewritten the DFE code. The use AXI(SP?), instead of the PLB bus. They plan to make this open source.
BNL has submitted all of the paperwork to make our boards open source.
BNL has ported over the EVR and Synchronous Data Interchange to the ZYNC FPGA. The new DFE is not yet completed.
Bob
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