Re: Read and Write errors with VME-EVR-300

["Shen, Guobao via Tech-talk" <tech-talk at aps.anl.gov>]

Heinz,
Any suggestion whether the problem is specific to some CPU boards, or it is a general issue to VME system?

Thanks,
Guobao

On 10/4/22, 6:34 AM, "Tech-talk on behalf of Heinz Junkes via Tech-talk" <tech-talk-bounces at aps.anl.gov on behalf of tech-talk at aps.anl.gov> wrote:

    Hello Ran Hong,
    I have similar problems in a constellation with MVME6100 and STRUCK SIS3316.

    I could solve the problem ( not elegant ) by using another (old) CPU as VME arbiter in slot 1
    and disabling the arbiter on the MVME6100 and plugging the CPU into slot 2.
    Heinz


    > On 4. Oct 2022, at 02:29, Hong, Ran via Tech-talk <tech-talk at aps.anl.gov> wrote:
    > 
    > Hello All,
    > 
    > I am testing a VME IOC with 1 VME-EVM-300 and 6 VME-EVR-300 boards. The CPU board is mvme-3100, and the driver is derived from mrfioc2:
    > https://github.com/epics-modules/mrfioc2
    > I experienced many errors like missing time stamp, incorrect GTX waveform, and so on. They all stem from issues when reading from or writing to VME registries using READ32 or WRITE32 in the driver. For example, in evrMrmApp/src/drvem.cpp line 803 to 806 for latching the timestamp, 
    > epicsUInt32
    >  ctrl=
    > READ32
    > (base,
    >  Control);
    > 
    > 
    > //
    > 
    >  Latch timestamp
    > 
    > WRITE32
    > (base,
    >  Control, ctrl|Control_tsltch);
    > 
    > 
    > It reads the control registry, modify the bit for timestamp latch, and write it back to the control registry. Occasionally, I saw the READ32 returns 0xffffffff, which is an invalid value for the control registry, and the subsequent WRITE32 results in a mess in the EVR.
    > 
    > Has anyone experienced similar issues? Any suggestions to prevent or mitigate the VME I/O errors?
    > 
    > Thanks!
    > 
    > Ran Hong