Argonne National Laboratory

Experimental Physics and
Industrial Control System

<19941995  1996  1997  1998  1999  2000  2001  2002  2003  2004  2005  2006  2007  2008  2009  2010  2011  2012  2013  2014  2015  2016  2017  2018  2019  2020  Index <19941995  1996  1997  1998  1999  2000  2001  2002  2003  2004  2005  2006  2007  2008  2009  2010  2011  2012  2013  2014  2015  2016  2017  2018  2019  2020 
<== Date ==> <== Thread ==>

Subject: Re: Logical Naming of Hardware Addresses
From: watson@cds002.cebaf.gov
Date: Wed, 25 May 94 09:19:19 -0400
anj@mail.ast.cam.ac.uk writes:

>The approach I am suggesting is to have a file on the host which is read at 
>initialisation and contains some form of Logical Name to Physical Address 
>translation table. 

Proliferation of files is a bad idea.  If you have enough reflective memory,
you could use dynamic allocation, and include a hash table in the reflective
memory to look up names.  All IOC's would first look up the name, and if it
did not exist, would add it dynamically.  A semaphore (soft or hard, depending
upon what the hardware supports) would protect the hash table.

Chip

Navigate by Date:
Prev: Logical Naming of Hardware Addresses Andrew Johnson
Next: Re: Logical Naming of Hardware Addresses Andrew Johnson
Index: <19941995  1996  1997  1998  1999  2000  2001  2002  2003  2004  2005  2006  2007  2008  2009  2010  2011  2012  2013  2014  2015  2016  2017  2018  2019  2020 
Navigate by Thread:
Prev: Logical Naming of Hardware Addresses Andrew Johnson
Next: Re: Logical Naming of Hardware Addresses Andrew Johnson
Index: <19941995  1996  1997  1998  1999  2000  2001  2002  2003  2004  2005  2006  2007  2008  2009  2010  2011  2012  2013  2014  2015  2016  2017  2018  2019  2020 
ANJ, 10 Aug 2010 Valid HTML 4.01! · Home · News · About · Base · Modules · Extensions · Distributions · Download ·
· Search · EPICS V4 · IRMIS · Talk · Bugs · Documents · Links · Licensing ·