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<== Date ==> <== Thread ==>

Subject: Re: Logical Naming of Hardware Addresses
From: Andrew Johnson <anj@mail.ast.cam.ac.uk>
Date: Wed, 25 May 1994 14:47:47 BST
On Wed, 25 May 94 09:19:19 -0400 watson@cds002.cebaf.gov wrote:

> anj@mail.ast.cam.ac.uk writes:
> 
> >The approach I am suggesting is to have a file on the host which is read at 
> >initialisation and contains some form of Logical Name to Physical Address 
> >translation table. 
> 
> Proliferation of files is a bad idea.  If you have enough reflective memory,
> you could use dynamic allocation, and include a hash table in the reflective
> memory to look up names.  All IOC's would first look up the name, and if it
> did not exist, would add it dynamically.  A semaphore (soft or hard, depending
> upon what the hardware supports) would protect the hash table.

I would prefer to use dynamic allocation, but I can't find a way of creating a 
semaphore in the Reflective Memory (a TAS can occur and succeed in several CPUs 
simultaneously), hence I can't use the shared data structures which would need a 
semaphore for protection.  

There is also the problem of initialising the memory, and what happens when one 
IOC is powered up later than the others so it misses out any write cycles which 
occurred before it was turned on.

I have come to the conclusion that I can't rely on control structures in the RM 
to tell me where the record boundaries are, so I have to get this information 
from elsewhere.

In my case the same name file would be shared by all the IOCs with RM cards in, 
so its not a large proliferation, but I guess the same might not be true if it 
were used for other devices.

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