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<== Date ==> <== Thread ==>

Subject: Power PC floating point underflow
From: wlupton@keck.hawaii.edu (William Lupton)
To: tech-talk@aps.anl.gov
Date: Thu, 22 Oct 1998 15:35:19 -1000
Dear all,

  We tracked down the Power PC floating point underflow reported a few
weeks ago by Kevin Tsubota to a piece of code (mea culpa) which was
under some circumstances using uninitialized double precision numbers
(off the stack) as the values of output links to other records' VAL
fields. When these records processed we got floating point underflows.

  We have run this code for a year or so on Force CPU/40s and Motorola
MVME-177s. This suggests to me that floating point underflow is by
default disabled or somehow handled differently on these boards. Can
anyone elucidate?

  The VxWorks documentation explicitly states that floating point
underflow is enabled by default on Power PCs. It also explains how to
disable it on a per-task basis. I do not see any equivalent description
for M680x0 processors.

  Overflows, underflows and divide by zeroes are all errors and it is
reasonable that they should cause exceptions. Would there be any
support, though, for providing an architecture-independent method for
controlling them (e.g. a hook routine that would be called whenever
EPICS created a task)?

  Thanks,

  William

Replies:
Re: Power PC floating point underflow Marty Kraimer

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