Experimental Physics and
Industrial Control System

Joe Sullivan <[email protected]> · Tue, 15 Dec 1998 16:58:53 -0600

John Winans solved this problem on the Motorola 680xx processors 
that we use at the APS (ie. MVME167 and MVME162). These boards use 
the VMEchip2 for memory decoding.

A set of A24 memory management fuctions were created. See John's 
inline comments below
.
.
/******************************************************************************
 *
 * A24 memory management routines. (JRW)
 *
 * A user may call sysA24MapRam() to place a chunk of memory in the
 * A24 memory space.  When this is done, an aligned malloc is done
 * on the specified size (after rounding up to power of 2) to get
 * the memory to map into A24-space.  If the malloc succeeds, then
 * the chunk of memory is mapped into A24 using VSAMSR2, and a memory
 * pool is created for future use with malloc and free -style management
 * calls.
 *

******************************************************************************/
.
.

These are the functions...
	sysA24MapRam() 
	sysA24Malloc()
	sysA24Free()

A24 address handling was also added to sysBustoLocalAdrs(). 

Let me know if you think having the source code would help you. 

"John A. Priller" wrote:
> Scanning through the tech-talk archives I found references to patching the
> WRS BSPs to allow A24 DMA access to work, but no details.  Is there anyone
> who's done that and gotten it to work (hopefully for a PPC board, but I'm
> willing to look at any examples at all)?
> 

Joe Sullivan 
Beamline Controls & Data Acquisition Group
Advanced Photon Source, Argonne National Lab
(630)252-8657

Experimental Physics and Industrial Control System

Experimental Physics and
Industrial Control System