For the mv167 we needed to make a change in sysLib.c (which configures the
VMEchip2) to allow for A24/D32 accesses. sysLib.c is in
vxworks/target/config/mv167, I assume that there is a similar file for the
mv162 though we do not use that board. In sysLib.c there is a section (in
the mv166/67/77 seriers) where this is being controlled, the original file
has:
/* set VMEbus std access and enable map */
*VMECHIP2_LBSAR2 = 0xf0fff000;
*VMECHIP2_LBSAR |= LBSAR2_AM_STD_USR_DATA |
LBSAR2_D16;
we modified this to be:
/* set VMEbus std access and enable map */
*VMECHIP2_LBSAR2 = 0xf0fff000;
*VMECHIP2_LBSAR &= ~LBSAR2_D16; /* for SIAM 7/31/97 */
*VMECHIP2_LBSAR |= LBSAR2_AM_STD_USR_DATA |
LBSAR2_D32;
/* for SIAM 7/31/97 */
*VMECHIP2_LBTVCR |= LBTVCR_EN2;
As you can see, we did this to support the SIAM. Hope this helps you.
Perry
On Fri, 3 Mar 2000, Burkhard W. Kolb wrote:
> Hi,
>
> I have a problem setting up a 162 cpu to work with the SIAM (Bira 7550) module.
> This module allows A24 access only. It has an Status register (32 bits)
> at its
> base address and then various 16bit registers at +4... addresses. As far
> as I
> understand the BSP for the 162 (in syslib.c) the VME access in A24 mode is
> word (16 bit) only. When the code accesses the statusregister with a long
> pointer the VMEchip2 is supposed to break this into 2 cycles of 16 bit and
> then fit the longword together from the two pieces, right?
> When I print out the status register contents I get 0xcd55ffff. On a VMEbus
> display I see the 0xffff and the last address being 0x00300002. But the word
> 0xcd55 is the (fixed) contents of the ID register of the module, at address
> 0x00300004.
> Something wrong in the way the registers are setup for the VMEchip2?
>
> Burkhard Kolb
> GSI Darmstadt
> HADES detector
>
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