Experimental Physics and
Industrial Control System

Kay-Uwe Kasemir <[email protected]> · Wed, 24 Jul 2002 11:10:35 -0600

Hello:

Some remarks on "cashing" w/ PPC boards and the universe-II chip.

I had problems within interrupt service routines on MVME2100 CPUs.
The ISR contained several VME reads and writes
to determine the cause of the interrupt and then clear it.

On the backplane analyzer, those "writes" sometimes showed up
with huge time intervals between them.
So the "clear interrupt" reached the board with a long delay.

Dave Thompson (ORNL) helped with the following.

The assumption was: The UniverseII chip keeps writes 
in a pipeline instead of flushing them to the VME bus.
And yes: There is no obvious "disable pipelining" register
on the Universe II.

This looks paranoid, but now my ISR seems to function all the time:
1) #define SYNC __asm__ volatile ("sync")
   then "SYNC" after writes to assert that
   the commands actually leave the CPU.
2) At the end of the ISR, add a dummy "read" to the addres
   of the last "write". That seems to flush the Universe-II write pipeline.

Thanks,
-Kay

At 09:42 AM 7/24/2002, Jeff Hill wrote:
>Also, make certain that your vxWorks BSP is configuring the MMU to turn
>off caching for device address spaces.
> -----Original Message-----
>> From: ahed aladwan [mailto:[email protected]]
>> according to Tundra
>> (universe chip, PCI - VME bridge) it is not possible to disable
>address
>> pipelining.

Experimental Physics and Industrial Control System

Experimental Physics and
Industrial Control System