Re: ISEG VHQ204L Driver (Really: PPC and VME)

[Kay-Uwe Kasemir <kasemir@lanl.gov>]

At 12:21 AM 7/25/2002, you wrote:
>Hi,
>
>we use on PPCs __asm__ volatile ("eieio"), which is the correct
>assembler instruction to make sure that the write has finished before
>the next read on VMEbus is executed.
>The same by the way is true for 68k archticture where the instruction
>would be "nop".

Hi:

Sounds like another way of forcing electrons out of the CPU
- if not even better than __asm__ volatile ("sync").

But what about the Universe II chip on most PPC boards
which has its own write pipeline?
Is there a "flush" register/command on it?
My experiments showed that a dummy read was needed after the
write & sync and my guess was: That's in order to make the UniverseII
flush the writes, because the CPU cache has already been overruled by
(1) sync or eieio
(2) the fact that the memory regions mapped to VME are configured as "not cacheable"
    in the vxWorks BSP's sysPhysMemDesc

Thanks,
-Kay