RE: Hytec DAC8402

["Sibley III, Coles" <sibley@ornl.gov>]

Thanks Eric,

 

It’s in D16 A32 address space, an IP module on a carrier board.

 

Our bus analyzer ran out of memory recording the read access’s after ~32 msec, every 1.37 usec.

Hytec Electroncs called and suspects a wrong status bit getting (or not) set.

 

Coles

 

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From: Eric Bjorklund [mailto:bjorklund@lanl.gov]
Sent: Thursday, June 16, 2005 6:49 PM
To: EPICS tech-talk
Subject: Re: Hytec DAC8402

 

Coles,

 

Where does the DAC8402 reside in I/O space? We had a similar problem with a serial driver in A32 space a few years ago. As near as we could tell, the hardware was working fine, but the register data seemed like it was being cached (even though it looked like the mapping registers in the BSP were disabling caching for A32 space). Our fix was to insert a

cacheInvalidate (DATA_CACHE, (void *)statadr, 12);

call into the loop. We never really figured out whether this defeated the hardware cache, or just broke the loop out of the CPU instruction pipeline, but it worked.

 

You might try a bus-analyzer to see how many reads you really are issuing to the DAC.

 

Hope this helps...

 

-Eric Bj.

 

On Jun 16, 2005, at 10:47 AM, Sibley III, Coles wrote:

 

Hello,

 

We are using a Hytec DAC8402 at SNS for our beam loss monitor reference. The driver uses far too much CPU time when we update 8 dacs every 5 seconds. In fact it goes to 100% cpu usage. The offending code is below. We can fix the code but the question is why does it take so long to set 16 register?

 

The 8402 can be set to uses registers (for a typical dac application) or memory (for arbitrary waveforms). We need the typical dac configuration, not the arbitrary waveforms.

 

We are using a Motorola MVME5100 cpu.

 

The wait count goes to 600000 in our case, as if statadr was not declared as volatile or the 512K of memory is getting loaded, not just the 16 registers. Our WAITLIM has to be set to 1000000.

 

   while(((*statadr&CSR_ARM) !=0) && waitcount < WAITLIM)waitcount++;

 

    if( waitcount < WAITLIM )

    {

        /* set dac value and rearm  */

        card->pMem->Data[signal]=val;

        *statadr |=CSR_ARM;

    }

 

The manual says:

“

While the unit is ARMed the DACs are constantly refreshed with the contents of the registers which can be changed during this time. There is a delay which is fixed of approximately 32us after ARM is set, before all the outputs change together.”

 

The problem seems to be that the ARM stays high far longer than seems reasonable, as the count rate indicates.

 

The initialization in st.cmd is:

Hy8402Configure(1,1,0,0,0,0,0,0)

Hy8402Configure(2,1,1,0,0,0,0,0)

 

 

Any suggestions?

 

Coles Sibley

SNS – ORNL

Controls Hardware Engineer

865-241-8055

sibley@sns.gov

 

 

 

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Eric Björklund

Los Alamos Neutron Science Center (LANSCE)

 

phone: 505-667-6031 email: bjo@lanl.gov

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