RE: devlib2 and asyn Pros/Cons

["Williams Jr., Ernest L." <ernesto@slac.stanford.edu>]

________________________________________
From: Johnson, Andrew N. [anj@aps.anl.gov]
Sent: Thursday, May 21, 2015 11:45 AM
To: Williams Jr., Ernest L.
Cc: Rivers, Mark L.; tech-talk@aps.anl.gov
Subject: Re: devlib2 and  asyn  Pros/Cons

Hi Earnest,

There is an epicsEndian.h header in 3.14 that tells you what your CPUs endianness is, and the MMIO features of devlib2 that have now been included in Base-3.15 do the necessary byte-swapping. If that doesn't answer your question then we probably don't understand what you're asking.
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Excellent. :)
Indeed, 3.15 has the goodies.



Cheers,
Ernest




- Andrew

--
Sent from my iPad

> On May 21, 2015, at 2:34 PM, Williams Jr., Ernest L. <ernesto@slac.stanford.edu> wrote:
>
>
>
> Sent from my iPhone
>
>> On May 21, 2015, at 10:32 AM, Mark Rivers <rivers@cars.uchicago.edu> wrote:
>>
>> Hi Ernest,
>>
>> I don't think it is really and either/or question with devlib2 and asyn.  At least for the drivers I've seen they work together.  For example I've written an asyn driver for the SIS3820, but it would be nice to have devlib2 functions to do OS-independent DMA with it.  So asyn drivers make calls to devlib2 functions for OS-independent access to the VME or PCI bus.
> What about endianness ?
> That would be also nice
>
>>
>> How does devlib2 get involved with Ethernet/RS-232 based devices?
> Not all, as far as I know
>
> But I think Michael Davidsaver or Till will chime in here :-)
>
> Cheers
> Ernest
>
>>
>> Mark
>>
>> ________________________________________
>> From: tech-talk-bounces@aps.anl.gov [tech-talk-bounces@aps.anl.gov] on behalf of Williams Jr., Ernest L. [ernesto@slac.stanford.edu]
>> Sent: Thursday, May 21, 2015 9:26 AM
>> To: tech-talk@aps.anl.gov
>> Subject: devlib2 and  asyn  Pros/Cons
>>
>> Hi everyone,
>>
>> We would like to go down a path of standardizing new EPICS drivers that we develop here at SLAC.
>>
>>
>> Can folks speak about pros/cons for using devlib2-based approach  versus an asyn-based approach for access
>> to (1) PCI bus access, VME64x CSR/CSR, and other memory-mapped devices; (2) ethernet/RS232 based; stream-based ?
>>
>>
>> Here at SLAC we have a module that Till wrote which addresses:
>> (1) memory and I/O barriers, (2) endianess
>> Is this something that belongs in or is now in EPICS BASE?
>>
>>
>>
>> Cheers,
>> Ernest
>