Experimental Physics and
Industrial Control System

"Ha, Kiman via Tech-talk" <[email protected]> · Mon, 11 Nov 2019 21:05:26 +0000

Hi Hinko,

Thanks for your information about the ESS uTCA AMC interface and XDMA  driver development status.
I think you are application is the PCIe XDMA bridge for the Kintex/Vertex Ultrascal/+ firmware for interface with uTCA CPU, which seems very good progress.

My application used zynq/zynq Ultrascal+ FPGA which called MPSoC core for standalone applications.(for me No PCIe, used HP port)
The  Xilinx provides axidma deriver as Kernel module, but we still need userspace DMA driver/library and epics device support.

We have own custom DMA driver for Zynq fpga but this version was not used Xilinx DMA IP core and Xilinx axidma Linux kernel driver(Non-standard concept). 
For the new development based on zynq Ultrascal+, I would like to more "generic version" it means used Xilinx AXI DMA IP core and Linux axidma driver.

I found several open-source the Xilinx axidma driver and userspace library for DMA data read/write, but still, I am thinking about how to communicate with epics device support.

Tim provides a good reference for the softGlue that used aSub recode to readout DMA data from epics device support. Thanks Tim.

Thanks,
Kiman

-----Original Message-----
From: Hinko Kocevar <[email protected]> 
Sent: Monday, November 11, 2019 4:04 AM
To: Ha, Kiman <[email protected]>; [email protected]
Subject: Re: Linux DMA driver and device support for Xilinx FPGA

> Does anyone have to experience generic DMA support for the  Xilinx Zynq or Zynq ultrascal+ core or have a plan for the development?

Not sure what you mean by "generic" DMA support. Couple of software and firmware developers here at ESS are working on a firmware using XDMA ip core, that is supported by Xilinx xdma kernel driver (sources online). Running on the Ultrascale FPGA (not zynq) on an AMC sitting in a uTCA crate. This means we are not developing our own DMA / PCIe core but utilizing Xilinx one, available free of charge.
Some preliminary tested are showing ~88% PCIe link utilization when transferring data in bulk over DMA; i.e. Gen3 4 lanes rate is ~3.5 GB/s card to host.

All of this is still in prototyping stage.

We have no EPICS driver for this, yet. The plan is to, first develop userpace library that would abstract away details and let the user work with clocks, triggers, data channels..; compared to to "raw FPGA registers". Then, the EPICS driver will be built on top of this userspace library.

//hinko
________________________________________
From: Tech-talk <[email protected]> on behalf of Ha, Kiman via Tech-talk <[email protected]>
Sent: Saturday, November 9, 2019 11:22:03 PM
To: [email protected]
Subject: Linux DMA driver and device support for Xilinx FPGA

Hello,

I am looking for the DMA driver and epics device support module for the Xilinx Zynq and Zynq ultrascal+ core.
Does anyone have to experience generic DMA support for the  Xilinx Zynq or Zynq ultrascal+ core or have a plan for the development?

For example, we developed four channel 500 MHz digitizer for the bunch by bunch beam position monitor (performance looks good, < 300 nm turn by tune position for the NSLS-II).
Currently, prototype supports an FPGA logic block ram (BRAM, 8 K/16 K * 16bit * 4, 500MHz clock rate) .
I have plan provides at least 1 M * 16bit * 4)  or 2 M points from the external DDR3/4 memory (FPGA side we implemented DMA core, but Linux part needs help) .
Because our physics group wants to minimum 1000 turns BxB position data.
If we have an epics device support, that's very valuable for many diagnostics applications, especially beam diagnostics and physics applications.

Thanks,
Kiman

Experimental Physics and Industrial Control System

Experimental Physics and
Industrial Control System