Experimental Physics and
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I got the driver from kristi luchini in SLAC, ftp.slac.stanford.edu But I have another preoblems with the ISEQ VHQ202 VME module: When the master (PPC MVME2304, vxWork 5.3.1) reads the data from the slave (A16, D16, address mod is 0x2D or 0x29), it seems that for some addresses the master get the data for the next address (+ 1 byte), using a logic analyzer to check the master read cycle (attached pdf file), I have noticed that because the master apply address pipelining (forcasting) and the slave dosen't latch the data (or address), I got wrong data. But what I can't understand why this happens only for some addresses but not all, espicialy the base address (status register) (ISEQ has no clue) Is it a bad design of the slave or there is something unclear for me in the master configuration, what is the situation with other labs who uses similar card model and different IOC, moreover according to Tundra (universe chip, PCI - VME bridge) it is not possible to disable address pipelining. I appreciate any suggestions. Best regards, Ahed Aladwan Leng, Yongbin wrote: Hi Guys,
Attachment:
vhq_read_cycle.pdf Attachment:
Read cycle_IEC821.pdf
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ANJ, 10 Aug 2010 |
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