Experimental Physics and
Industrial Control System

Tony Cox - (415)926-3105 <[email protected]> · Fri, 10 Feb 1995 10:18:13 PST

John writes:-

>I agree with your logic flow 100% WRT internal data structure sizes and
>implied sizes and so on.  However, I would rather see the IOC data structures
>completely rethought.  Let them become what ever the native machine wants,
>clean up the int <-> void* assignments, and simply do all transfers of the
>database in ASCII.  This would allow all the iocCore code to compile into
>what ever byte size and sex it wants... who cares?  Lose the 'for the
>sake of speed' code that is not portable... or at least provide ifdef'd
>alternates so that EPICS can be made portable.

Perhaps I was not as clear as I should have been. The problems wrt endianness
and word sizes are of critical importance only for data structures which are
shared between different architectures. Since EPICS does a good job of
encapsulating inter-machine interactions, this really only applies to
channel access & the record support layers. Below that, as you say below, 
there will always be machine dependencies. I suppose one might try to make a
case on esthetic grounds for commonality here, but I wouldn't like to do it...!

But can we really lose code which is there "for the sake of speed"? Full
blooded conversion to ASCII data transfers would result in around 4x the amount
of data bring transferred over the EtherNet at IOC startup. No problem for 
small sites, but what about APS and CEBAF???

>
>That would leave the CA code... it has to be fixed anyway.
>

Jeff & I have found problems in CA code which may be fixed in the next day or
so. CA will need to be updated for the general heterogeneous environment (where
there are both little- and big- endian IOC and hosts systems coexisting in the
same control system) to prevent unnecessary byte swapping.

>There is, however, going to be some trouble with the drivers.  I am not sure
>that they can be made as portable.  They will ALWAYS require an exact byte sex
>and size when they are defining their register maps.  I suppose your typedef
>idea would be a good start at it.  But there is always going to be timing
>and BSP-dependancies that some of them will not be able to overcome.
>

Agreed!
Tony Cox

--------------------------------------------------------------------------------
Dr Anthony D Cox
Computer Systems Specialist
Stanford Synchrotron Radiation Laboratory
Stanford Linear Accelerator Center
MS 69, Box 4349
Stanford CA 94305
[email protected]
--------------------------------------------------------------------------------

Experimental Physics and Industrial Control System

Experimental Physics and
Industrial Control System