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<== Date ==> <== Thread ==>

Subject: The "LOGIC" record
From: mcn@aps.anl.gov (Matthew Needes (LANL))
To: tech-talk@aps.anl.gov
Date: Fri, 25 Aug 1995 08:25:12 -0500
A new record will be available in the R3.12.2 edif _extension_: the "logic"
record.  Right now it is experimental and will not be installed in EPICS
base.

The "logic" record is similar to the PAL record in that it can represent
logic equations and finite state machines.  However it differs from the PAL
record (and other records) in that:

a)  "Logic" is graphically defined within CAPFAST.  Hierarchical constructs
	are supported.  Basically you draw and/or/xor blocks (almost exactly
	like hardware design), connect them together to themselves or other
	symbols representing the inputs and outputs of the logic record.  The
	record has 16 input links and 16 output value fields.  These fields
	are of type "double".

b)  "Logic" supports more than just boolean data types, and more than
	just boolean operations.  This is because the the logic record uses
	C code compiled modules, rather than performing bitwise logic
	operations on data arrays, which is what the PAL record currently
	does.

     Logic supports addition and comparison blocks that can operate on both
	 integer and floating point types (like labView).

c)  "Logic" allows a maximum of 16 output flip-flops (registers) and an
	arbitrary number of internal flip-flops, whereas the PAL record
	allows a maximum of 12 output flip-flops only.  Flip-flops are
	currently type "double", but I suspect this will change in future
	revisions.  (yes, a "double" flip-flop, similar to a register).
	The "logic" record only allows a maximum of 16 OUTPUT flip-flops.
	The unlimited number is for internal flip-flops only.

d)  "Logic" currently lacks an off-line logic simulator.  However, it should
	be an easy task to write one.

e)  The "logic" record is the only record that may have functional hierarchy
	underneath instances of it.  But even this is optional, because you
	can link any logic record to any hierarchical logic definition.

Two executables, a symbol library, and an example build script are provided
in the distribution.  An example set of schematics (lib/example/elogic.sch and
lib/example/test.sch) are also provided to get you started.

The conversion of schematics to object code is a four step process:

	sch2edif -  Converts the schematic hierarchy to a single hierarchical
			EDIF file.
	edif2lnf -  Converts the "logic" edif file into an LNF file,
				(LNF = Logic Netlist Format)
	lnf2c    -  Converts the flattened LNF file into a C file.
	make	 -  Creates objects from C files.

lnf2c uses another file called "e2c.def" that specifies what C code is
generated for the logic blocks on the schematic (see lib/e2c.def).  It
should be "self-explanatory" how to add functions to this file.  If you
make a mistake in e2c.def lnf2c should provide you with a warning.

Supported compiler blocks:

	INTERNAL FLIP-FLOP (REGISTER) -  Saves internal state bits
				(doubles), not seen on outputs.
	OUTPUT FLIP-FLOP   -  Register output that corresponds to an
				output field of the record.  All outputs
				must be registered.
	INPUT BLOCK        -  This block represents a value retrieved through
				the logic record's input links.

	(Digital blocks)
	NOR / OR / XOR / XNOR / AND / NAND / INVERTER
		(most logical blocks are available in 2/3/4 input versions)

	MULTIPLEXER	   -  Acts as a logical IF-statement.

	(Analog blocks)
	PLUS / MINUS / MULT / DIVIDE

	(Analog -> digital blocks)
	LESS THAN / GTHAN / LTEQ / GTEQ / EQ / NEQ / etc.  (comparisons)
	HYSTERESIS BLOCK   -  Logic threshold detector (similar to a PAL record
				input).  This block is actually a single level
				hierarchical schematic with a flip-flop that
				remembers the previous state.

Hopefully the use of this record can solve some state-dependent problems
directly in the EPICS database.  In some cases this record may serve as
an alternative to the sequence programs, whose execution isn't tightly
coupled to database execution.

Again, this code is bundled with the "edif" extension in R3.12.2.  This week
I can provide prereleases of this code to anyone interested in using it or
adding extensions to it (suggested extensions are in E2C_TODO).  Remember that
this code is "experimental" and will be unsupported unless there is sufficient
interest (any volunteers ?).

Well, I'll be leaving for Georgia in a few weeks.  It's been real-time.

Y'all be good now, hear !
	Matt


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