Re: Q: NI-1014 GPIB board with Force CPU40.

[Kazuro FURUKAWA <furukawa@kek.jp>]

Hello Yamamoto-san,

I'm sorry for my late message.

>>> In message <199509051259.VAA01788@kekux.kek.jp> ,  Noboru Yamamoto <yamamoto@acsad1.kek.jp>  wrote;

> After I sent a question to tech-talk, we found the following fact:
> 
> 	1) NI-1014 DMA can access VME address in A24 mode.
> 	2) To accesse Main memory on FORCE cpu40 via VME bus, address mode
> should be A32 mode.
> 
> These facts  means that the standard GPIB support routines in EPICS does not
> work for this combination of boards. We happened to have memory board for VME
> bus and allocated buffer space GPIB driver on this memory board. After that,
> GPIB support routines are working.

Force CPU40 has A24 slave capability, while CPU30 does not.  
Actually the A24 slave capability is implemented on an external 
circuit outside VME gate array (FGA-002) for CPU30/40.  Thus 
it isn't explained in the documentation of FGA-002 but in one 
of CPU-40.

I use this sort of code fragment (on OS9) to initialize A24 
slave access for A24 DMA. 

	p = (uchar *)0xff800c00;	/* pointer to PI/T1 */
	*(p+0x03) = 0xff;		/* PB all output,        PBDDR */
	*(p+0x09) = 0x80;		/* upper address in A24, PBDR */
	p = (uchar *)0xff800e00;	/* pointer to PI/T2 */
	*(p+0x04) = 0xa8;		/* PC7 output,           PCDDR */
	*(p+0x0c) = 0x7e;		/* enable A24 slave,     PCDR */

This way, you may eliminate an external memory board.

Regards, Kazuro.
-----
$B8E@n(B $BOBO/(B,  Kazuro FURUKAWA,  KEK-Linac  <furukawa@kek.jp>
 Natl. Lab. for High Energy Physics (KEK), Japan
 Telephone: +81-298-64-5694,  Facsimile: +81-298-64-7529