Experimental Physics and
Industrial Control System

"Leicester, PJ (Pete)" <[email protected]> · Tue, 5 Aug 2008 16:33:13 +0100

We are looking to collect data at a fixed clock rate starting and
stopping on the gate signal. The gate signal will however repeat so the
ADC needs to be immediately ready to collect data on the next gate. We
need to be able to identify which gate the data was collected in. If we
get an interrupt at the end of each gate then we should have sufficient
time to get the data off the ADC before the next gate period.

The Ip330 may well be able to do this with some external logic but I was
hoping to find a simple in one solution.

Thanks
Pete

-----Original Message-----
From: Mark Rivers [mailto:[email protected]] 
Sent: 05 August 2008 14:24
To: Kalantari Babak; Leicester, PJ (Pete)
Cc: [email protected]
Subject: RE: Gated ADC

Pete,

I am not clear on exactly what you want.  Do you want to 1) collect one
sample per transition of the gate signal, or do you want to 2) collect
data at a fixed clock rate but start and stop acquisition with a gate
signal?  The IP-330 may do what you want, depending on what mode you use
it in.  If mode 2) is what you want then you could always use some
external logic to gate an external clock source off and on.

Mark

-----Original Message-----
From: [email protected] on behalf of Kalantari Babak
Sent: Tue 8/5/2008 5:49 AM
To: Leicester, PJ (Pete)
Cc: [email protected]
Subject: RE: Gated ADC

Hi Pete,

I think 8401 Hytec IP module together with 8002 or 8004 (supports BLT as
well) carrier is what you are looking for. Take a look at
http://www.hytec-electronics.co.uk/8401UTM_ISS12.pdf 

It has all the features you mentioned. I would use the INHIBIT input as
the hardware gate. If the inhibit input is taken low the memory update
is stopped and an interrupt is invoked (if enabled).

We have a driver for waveform but it may require very little
modification only in the interrupt service routine to properly handle
memory inhibit interrupts.

Let me know if you need the driver.

Regards,

Babak

________________________________

From: [email protected]
[mailto:[email protected]] On Behalf Of Leicester, PJ (Pete)
Sent: Dienstag, 5. August 2008 10:20
To: [email protected]
Subject: Gated ADC

1) Data collection controlled by a hardware gate signal such that data
is collected into a buffer when the gate is enabled and when the gate is
disabled an interrupt is generated so the data can be transferred into
an I/O Intr processed waveform (or similar) record.

2) Sample rate up to at the least 10KHz but preferably 100KHz, and an
absolute minimum of 16 bit.

3) Epics support for waveform record (or MCA or similar).

4) Preferably packaged as an IP module but a VME card would be OK.

Note that the essential feature is the gating of collection on the
hardware signal. We do not want to trigger and collect a fixed number of
samples (most ADC's do this). 

Any suggestions would be gratefully received.

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Experimental Physics and Industrial Control System

Experimental Physics and
Industrial Control System