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<== Date ==> <== Thread ==>

Subject: Re: Question about 85XX dual core CPU board for VxWorks/EPICS
From: 王林 <wanglin@ihep.ac.cn>
To: "Andrew Johnson" <anj@aps.anl.gov>
Cc: tech-talk@aps.anl.gov
Date: Mon, 25 Jun 2012 22:06:26 +0800
Hello Andrew,

Sorry for replying so late. Our processor board CPCI-6200 (MPC8572 dual core) has arrived last week. In UP mode, it works fine for a EPICS example application, as well as the demo EPICS driver for our cPCI I/O device.

In SMP mode, I replace intLock() with spinLockIsrTake(), intUnlock() with spinLockIsrGive() in osdInterrupt.c, and replace taskVarAdd / taskVarDelete pair for papTSD with a __thread specifier (INCLUCE_TLS component) in osdThread.c. The file CONFIG.Common.vxWorks-mpc8572, osdInterrupt.c and osdThread.c are as I attached. But I am not sure whether this change is appropriate.

For both the EPICS example application and the demo EPICS driver for our cPCI I/O device, it seems to work, the loading of the example application is also attached. Actually, I just make it work, since I do not know much of mechanisms of EPICS core, and I am not sure whether potential problems will occur in future. As you mentioned, there should be many assumptions that fit for UP but not SMP in EPICS core, such as implicit synchronsization of task with priority and public variables that need memory barrier. 

So, which places of EPICS base should be modified for SMP support? And how to test them?

My development environment is vxWorks6.8.2 / EPICS BASE 3.14.12.1 / CPCI-6200 / RHEL4.8./ a customized I/O device.. 


Thanks,
Lin Wang
 

----- Original Message ----- 
From: "Andrew Johnson" <anj@aps.anl.gov>
To: <tech-talk@aps.anl.gov>
Sent: Friday, April 06, 2012 1:27 AM
Subject: Re: Question about 85XX dual core CPU board for VxWorks/EPICS


> Hi,
> 
> On 2012-04-05 王林 wrote:
>> When I ask questions the year before last, I mentioned we wanted to chose
>>  CPCI-6200 (Dual core MPC8572, PCIe) for our cPCI VxWorks/EPICS system.
>>  Actually, for the sake of reducing the difficuly, we chose CPCI-6020
>>  (MPC7410, PCI) at that time. But these days, we want to purchase this
>>  CPCI-6200 for our alternative choice of cPCI CPU board, and try to run
>>  EPICS on vxWorks 6.6 or 6.8, AMP or SMP. But I am not sure whether it is
>>  possible to run EPICS on dual core 85XX CPU, and whether there are other
>>  important issues that I should think about. Any advice?
> 
> It might be possible to run current versions of EPICS on that CPU if it can 
> support a UP build of vxWorks, but they would not make use of the second core.  
> The current vxWorks support routines for EPICS Base were written long before 
> Wind River decided to support SMP, and thus they make many assumptions which 
> are incorrect on an SMP system.  For example they assume that within an 
> intLock() ... intUnlock() pair no other EPICS code can be running, which is 
> true on a UP system but not on SMP.
> 
> If you have the time to write a new vxWorks-SMP support layer for EPICS then I 
> would be happy to work with you to get your new code accepted into a future 
> version of the EPICS distribution, but it would probably take you several 
> months of C development work to create and test the new support code.  I 
> believe there are other EPICS sites that are also interested in SMP support, 
> but nobody has offered to work on this yet.
> 
> I don't know how the AMP mode works; if it allows you to run programs written 
> for the original UP vxWorks API then you should be able to run an IOC on the 
> board in this mode.  You might even be able to run two separate IOCs on the 
> two cores if the AMP mode makes the board look like two completely independent 
> computers, but you would have to be very careful with the device drivers you 
> load so that you don't have the two machines trying to control the same piece 
> of hardware at the same time.
> 
> - Andrew
> -- 
> Never interrupt your enemy when he is making a mistake.
> -- Napoleon Bonaparte
>

Attachment: osdThread.c
Description: Binary data

Attachment: CONFIG.Common.vxWorks-mpc8572
Description: Binary data

Press any key to stop auto-boot...
 1
auto-booting...


boot device          : motetsec
unit number          : 0
processor number     : 0
host name            : console101
file name            : /home/vxworks/bootdir/vxWorks_6.8_6200_SMP
inet on ethernet (e) : 192.168.206.108:ffffff00
host inet (h)        : 192.168.206.74
user (u)             : vxworks
flags (f)            : 0x0
target name (tn)     : cpci6200

Loading... 1927728 + 245360
Starting at 0x100000...

Loading symbol table from console101:/home/vxworks/bootdir/vxWorks_6.8_6200_SMP.sym ...done


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 ]]]]]]]]]]]]]]]]]]]]]]]]]]]]]       Development System
 ]]]]]]]]]]]]]]]]]]]]]]]]]]]]
 ]]]]]]]]]]]]]]]]]]]]]]]]]]]       VxWorks 6.8 SMP
 ]]]]]]]]]]]]]]]]]]]]]]]]]]       KERNEL: WIND version 2.13
 ]]]]]]]]]]]]]]]]]]]]]]]]]       Copyright Wind River Systems, Inc., 1984-2009

 CPU: Emerson CPCI6200-13-2G       - MPC8572 (SMP[2]).  Processor #0.
 Memory Size: 0x7fdff000.  BSP version 2.0/0.
 Created: Jun 24 2012, 15:18:00
 ED&R Policy Mode: Deployed
 WDB Comm Type: WDB_COMM_END
 WDB: Ready.

->
->
-> vxCpuConfiguredGet
value = 2 = 0x2
-> vxCpuEnabledGet
value = 3 = 0x3
->
-> </home/cpci6200/epicsApp_smp/iocBoot/iocexample/st.cmd
## Example vxWorks startup file

## The following is needed if your board support package doesn't at boot time
## automatically cd to the directory containing its startup script

cd "/home/cpci6200/epicsApp_smp"
value = 0 = 0x0

## You may have to change example to something else
## everywhere it appears in this file
ld <bin/vxWorks-mpc8572/example.munch
value = 154279952 = 0x9322010

## Register all support components
dbLoadDatabase "dbd/example.dbd"
value = 0 = 0x0
example_registerRecordDeviceDriver pdbbase
value = 0 = 0x0

## Load record instances
dbLoadTemplate "db/user.substitutions"
value = 0 = 0x0
dbLoadRecords "db/dbSubExample.db", "user=cpci6200"
value = 0 = 0x0

## Set this to see messages from mySub
#mySubDebug = 1

## Run this to trace the stages of iocInit
#traceIocInit

iocInit
Starting iocInit
############################################################################
## EPICS R3.14.12.1 $Date: Tue 2011-04-26 15:36:19 -0500$
## EPICS Base built Jun 25 2012
############################################################################
iocRun: All initialization complete
value = 0 = 0x0

## Start any sequence programs
#seq &sncExample, "user=cpci6200"
->
-> dbl
cpci6200:ai1
cpci6200:ai2
cpci6200:ai3
cpci6200:aiExample
cpci6200:aiExample1
cpci6200:aiExample2
cpci6200:aiExample3
cpci6200:aSubExample
cpci6200:calc1
cpci6200:calc2
cpci6200:calc3
cpci6200:calcExample
cpci6200:calcExample1
cpci6200:calcExample2
cpci6200:calcExample3
cpci6200:compressExample
cpci6200:subExample
cpci6200:xxxExample
value = 0 = 0x0
->
-> dbgf "cpci6200:calc1"
DBR_DOUBLE:         6
value = 0 = 0x0
-> dbgf "cpci6200:calc1"
DBR_DOUBLE:         7
value = 0 = 0x0
-> dbgf "cpci6200:calc1"
DBR_DOUBLE:         9
value = 0 = 0x0
-> dbgf "cpci6200:calc1"
DBR_DOUBLE:         0
value = 0 = 0x0
-> dbgf "cpci6200:calc1"
DBR_DOUBLE:         2
value = 0 = 0x0
->
->

Attachment: osdInterrupt.c
Description: Binary data


References:
Question about 85XX dual core CPU board for VxWorks/EPICS 王林
Re: Question about 85XX dual core CPU board for VxWorks/EPICS Andrew Johnson

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