1994 1995 1996 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 <2014> 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024 | Index | 1994 1995 1996 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 <2014> 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024 |
<== Date ==> | <== Thread ==> |
---|
Subject: | Re: Newport XPS-Q8 and Motor Record - armv5teb architecture |
From: | Torsten Bögershausen <[email protected]> |
To: | "Johnson, Andrew N." <[email protected]>, "Rivers, Mark L." <[email protected]> |
Cc: | "[email protected]" <[email protected]>, Tonia Batten <[email protected]> |
Date: | Thu, 8 May 2014 08:13:42 +0200 |
On 5/7/14 11:32 PM, Johnson, Andrew N. wrote:
Hi Mark, You could try adding a call to the gcc built-in routine __sync_synchronize(); after the last write to the asynUser structure. This implements a full memory barrier, which is equivalent to the two memory barriers inside the mutex operations. If this fixes it for ARM there is probably a better solution, but this will at least identify if this is the cause of the problem.
This would be needed on a multi-core system. What system is in use ? single core or multi core? I just got the motor simulator working on the Raspberry PI, (after some days of debugging) The trick was to use this block in motorApp/MotorSrc/motor.h: ============== /* Define, from top to bottom, how bit fields are packed. */ /* This works for gnu, SunPro, MS Visual C. */ #include <epicsEndian.h> #if (EPICS_BYTE_ORDER == EPICS_ENDIAN_LITTLE) #define LSB_First (TRUE) #warning LSB_First #endif #if (EPICS_BYTE_ORDER == EPICS_ENDIAN_BIG) #define MSB_First (TRUE) #warning MSB_First #endif =============== What do you get when you compile with this change ? MSB_First or LSB_First ?