RE: Newport XPS-Q8 and Motor Record - armv5teb architecture

[Mark Rivers <rivers@cars.uchicago.edu>]

I don't think this has anything to do with the problem we are seeing on the ARM5.  

The problem we are seeing does not have to do with passing the status bits to the motor record, it has to do with passing information in pasynUser->userData.  This is an asyn issue, not a motor record issue.

Mark


-----Original Message-----
From: tech-talk-bounces@aps.anl.gov [mailto:tech-talk-bounces@aps.anl.gov] On Behalf Of J. Lewis Muir
Sent: Wednesday, May 07, 2014 11:29 AM
To: tech-talk@aps.anl.gov
Subject: Re: Newport XPS-Q8 and Motor Record - armv5teb architecture

On 5/7/14, 11:01 AM, Jens Eden wrote:
> I don't know if this is the cause of the problem, but even on a
> single architecture, you will need a correct entry in this switch in
> motorApp/MotorSrc/motor.h

Jens posted about this to the list in February:

  http://www.aps.anl.gov/epics/tech-talk/2014/msg00158.php

>From that thread, it sounds like the motor module needs some work to
eliminate assumptions about, as Till Straumann wrote, "what storage unit
the compiler uses, how adjacent bits are packed across a storage-unit
boundary and in what order bits are allocated (LSB->MSB or MSB->LSB)."

Lewis