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<== Date ==> <== Thread ==>

Subject: Re: Newport XPS-Q8 and Motor Record - armv5teb architecture
From: "J. Lewis Muir" <jlmuir@imca-cat.org>
To: <tech-talk@aps.anl.gov>
Date: Wed, 7 May 2014 11:28:37 -0500
On 5/7/14, 11:01 AM, Jens Eden wrote:
> I don't know if this is the cause of the problem, but even on a
> single architecture, you will need a correct entry in this switch in
> motorApp/MotorSrc/motor.h

Jens posted about this to the list in February:

  http://www.aps.anl.gov/epics/tech-talk/2014/msg00158.php

>From that thread, it sounds like the motor module needs some work to
eliminate assumptions about, as Till Straumann wrote, "what storage unit
the compiler uses, how adjacent bits are packed across a storage-unit
boundary and in what order bits are allocated (LSB->MSB or MSB->LSB)."

Lewis


Replies:
RE: Newport XPS-Q8 and Motor Record - armv5teb architecture Mark Rivers
References:
RE: Newport XPS-Q8 and Motor Record - armv5teb architecture Mark Rivers
Re: Newport XPS-Q8 and Motor Record - armv5teb architecture J. Lewis Muir
Re: Newport XPS-Q8 and Motor Record - armv5teb architecture Stephen Beckwith
RE: Newport XPS-Q8 and Motor Record - armv5teb architecture Mark Rivers
Re: Newport XPS-Q8 and Motor Record - armv5teb architecture Stephen Beckwith
RE: Newport XPS-Q8 and Motor Record - armv5teb architecture Mark Rivers
Re: Newport XPS-Q8 and Motor Record - armv5teb architecture Jens Eden

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