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<== Date ==> <== Thread ==>

Subject: Re: Newport XPS-Q8 and Motor Record - armv5teb architecture
From: "Johnson, Andrew N." <anj@aps.anl.gov>
To: "Rivers, Mark L." <rivers@cars.uchicago.edu>
Cc: "tech-talk@aps.anl.gov" <tech-talk@aps.anl.gov>
Date: Wed, 7 May 2014 17:05:50 +0000
Mark,

What thread synchronization is used between the two tasks that are seeing different data? The ARM memory model is stricter than the Intel one, so the code must release a mutex after writing to shared data, and take a mutex before reading from shared data. It is even possible that the epicsRingBuffer code doesn't properly follow the ARM rules, I would try running the relevant libCom tests to check that. I can't research anything more about it right now (I'm on vacation), but it's something you might want to double check.

- Andrew

-- 
Sent from my iPad

> On May 7, 2014, at 6:34 PM, "Mark Rivers" <rivers@cars.uchicago.edu> wrote:
> 
> I don't think this has anything to do with the problem we are seeing on the ARM5.  
> 
> The problem we are seeing does not have to do with passing the status bits to the motor record, it has to do with passing information in pasynUser->userData.  This is an asyn issue, not a motor record issue.
> 
> Mark
> 
> 
> -----Original Message-----
> From: tech-talk-bounces@aps.anl.gov [mailto:tech-talk-bounces@aps.anl.gov] On Behalf Of J. Lewis Muir
> Sent: Wednesday, May 07, 2014 11:29 AM
> To: tech-talk@aps.anl.gov
> Subject: Re: Newport XPS-Q8 and Motor Record - armv5teb architecture
> 
>> On 5/7/14, 11:01 AM, Jens Eden wrote:
>> I don't know if this is the cause of the problem, but even on a
>> single architecture, you will need a correct entry in this switch in
>> motorApp/MotorSrc/motor.h
> 
> Jens posted about this to the list in February:
> 
>  http://www.aps.anl.gov/epics/tech-talk/2014/msg00158.php
> 
> From that thread, it sounds like the motor module needs some work to
> eliminate assumptions about, as Till Straumann wrote, "what storage unit
> the compiler uses, how adjacent bits are packed across a storage-unit
> boundary and in what order bits are allocated (LSB->MSB or MSB->LSB)."
> 
> Lewis
> 



Replies:
RE: Newport XPS-Q8 and Motor Record - armv5teb architecture Mark Rivers
References:
RE: Newport XPS-Q8 and Motor Record - armv5teb architecture Mark Rivers
Re: Newport XPS-Q8 and Motor Record - armv5teb architecture J. Lewis Muir
Re: Newport XPS-Q8 and Motor Record - armv5teb architecture Stephen Beckwith
RE: Newport XPS-Q8 and Motor Record - armv5teb architecture Mark Rivers
Re: Newport XPS-Q8 and Motor Record - armv5teb architecture Stephen Beckwith
RE: Newport XPS-Q8 and Motor Record - armv5teb architecture Mark Rivers
Re: Newport XPS-Q8 and Motor Record - armv5teb architecture Jens Eden
Re: Newport XPS-Q8 and Motor Record - armv5teb architecture J. Lewis Muir
RE: Newport XPS-Q8 and Motor Record - armv5teb architecture Mark Rivers

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