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+ Could not connect to EPICS home most of the time Aravamuthan Govindan
3
+ build multiple tops? Geoff Savage
2
− Moxa N-Port, ASYN and IOC Exit John Dobbins
    Re: Moxa N-Port, ASYN and IOC Exit Emmanuel Mayssat
        Re: Moxa N-Port, ASYN and IOC Exit John William Sinclair
2
+ sequencer under linux questions Dennis Nicklaus
1
+ incorrect time stamp for one record in an IOC Geoff Savage
1
+ Problem building base 3.14.8.2 on Win32 Douglas Pearson
5
+ Deadlock when using asyn? Rees, NP (Nick)
4
  new opportunity at Gemini Observatory Matthieu Bec  
+ Devices Which Send Unsolicited Messages Steven Banks
2
+ Smooth transition from medm to edm Emmanuel Mayssat
1
+ VME Bus Error handling on MVME3100 and 6100 boards Andrew Johnson
27
+ Porting EPICS to NetBSD David Dudley
8
+ looking for OSI version of epid record Dayle Kotturi
9
+ Original Motorola MVME 167 PROM Jiro Fujita
8
  EPICS Web Mirror How-To Ralph Lange  
+ MVME5500/Kate Feng wrote : > Anyway, the reason why I wanted to > clarify is that there is a cavet about the MVME5500 board, which is > due to its Discovery I system controller. It is a different issue fromwhat was discussed about the dummy read. > * Some PCI devices require Synchronization Barriers or PCI ordering > * for . For example, the VME-OMS58 motor controller we > * used at NSLS requires either enhanced CPU Synchronization Barrier > * or PCI-ordering (only one mechanism is allowed) for the PCI-write. > * The PCI-ordering simply implements a PCI conMVME5500/100 PCI sync. (was Re: Dev lib off-board register access) Kate Feng
1
  MVME5500/6100 PCI sync (was Re: Dev lib off-board register access) Kate Feng  
+ want to run my ioc in Amida Simputer btanu
3
+ Dev Asyn and Cygwin/Win IOCs , Modbus and scheduling. Bill Nolan
7
+ Re: VCCT and CA sniffer Ned Arnold
9
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