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<== Date ==> <== Thread ==>
Subject: Re: Dev lib off-board register access
From: Andrew Johnson <[email protected]>
To: Jukka Pietarinen <[email protected]>
Cc: Eric Bjorklund <[email protected]>, EPICS tech-talk <[email protected]>
Date: Fri, 14 Jul 2006 12:03:06 -0500
Jukka Pietarinen wrote:

I believe it has to be the same register the write was targeted at. I

It shouldn't be - the Universe-2 User Manual says explicitly in section 2.3.3.4: "Any PCI master attempting coupled transactions is retried while the TXFIFO contains data." A read is always a coupled transaction, thus any CPU read from the VMEbus should cause a delay while the TXFIFO is drained. I conclude that your problem is most likely not caused by the Universe-2 chip itself.

And this is what I see on the bus, which is really not what I wanted:

Read from pEr->Control
Read from pEr->RamData
Read from pEr->RamData
Write to pEr->Control
Read from pEr->RamData
Write to pEr->RamAddr
Read from pEr->RamData
Write to pEr->RamAddr
Write to pEr->RamAddr
Write to pEr->RamAddr

Is your A16 master window marked as Guarded in the sysPhysMemDesc[] table (in sysLib.c)? I can't think of any other explanation for the behaviour you were seeing.

- Andrew
--
Not everything that can be counted counts,
and not everything that counts can be counted.
  -- Albert Einstein
References:
Dev lib off-board register access Rees, NP (Nick)
Re: Dev lib off-board register access Dirk Zimoch
Re: Dev lib off-board register access Eric Bjorklund
Re: Dev lib off-board register access Kate Feng
Re: Dev lib off-board register access Eric Bjorklund
Re: Dev lib off-board register access Jukka Pietarinen
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