RE: motorRecord on linux-arm

[Mark Rivers <rivers@cars.uchicago.edu>]

This has been an ongoing headache every time a new EPICS architecture appears, and if it works to use epicsEndian.h then that should definitely be done.

Mark

________________________________________
From: tech-talk-bounces@aps.anl.gov [tech-talk-bounces@aps.anl.gov] on behalf of Jens.Eden@ptb.de [Jens.Eden@ptb.de]
Sent: Friday, February 07, 2014 9:21 AM
To: tech-talk@aps.anl.gov
Subject: motorRecord on linux-arm

I recently tried to run a motor on a Raspberry Pi and found that the DMOV
field would never
return to 1 after the move completed. The reason is, that the following
cpu-architecture
switch in motor.h doesn't have an entry for armv6

#if defined(_WIN32) || defined(_M_IX86) || defined(_X86_)
    #define LSB_First (TRUE)  /* LSB is packed first. */
#elif defined(__i386__) || defined(_armv4l_) || defined(_X86_64_) ||
defined(__APPLE__)
    #define LSB_First (TRUE)  /* LSB is packed first. */
#elif defined(i386)
    #define LSB_First (TRUE)  /* LSB is packed first. */
#elif defined(sparc) || defined(m68k) || defined(powerpc)
    #define MSB_First (TRUE)  /* MSB is packed first. */
#elif (CPU == PPC604) || (CPU == PPC603) || (CPU == PPC85XX) || (CPU ==
MC68040) || (CPU == PPC32)
    #define MSB_First (TRUE)  /* MSB is packed first. */
#else
    #error: unknown bit order!
#endif

Since (CPU == PPC604) is true for all cases where CPU is undefined, the
arm compiler did not
fall through to the error message in the else case.

I suggest to remove the switch and replace the occurrence of  MSB_First
with the EPICS
provided endianness switch:
+#include <epicsEndian.h>

-#ifdef MSB_First
+#if (EPICS_BYTE_ORDER == EPICS_ENDIAN_BIG)

Jens